List of Tables
-
Bridge chip clock-related configuration pins and descriptions
-
Bridge chip interrupt controller interrupt source assignment
-
HT message packet interrupt vector configuration register 10
-
HT message packet interrupt vector configuration register 11
-
HT message packet interrupt vector configuration register 12
-
HT message packet interrupt vector configuration register 13
-
HT message packet interrupt vector configuration register 14
-
HT message packet interrupt vector configuration register 15
-
HT message packet interrupt vector configuration register 16
-
HT message packet interrupt vector configuration register 17
-
HT message packet interrupt vector configuration register 18
-
Interrupts routed to INTn1 are in the service status segister 1
-
Interrupts routed to INTn1 are in the service status segister 2
-
The physical address composition of the I2C module internal registers
-
The physical address composition of the PWM controller internal registers
-
The physical address composition of the ACPI controller internal registers
-
The physical address composition of the RTC module internal registers
-
The physical address composition of the GPIO module internal registers
-
Correspondence between the I2C pins of the DVO and the control registers
-
Configuration methods and control ports supported by
PCIE_F0 -
Configuration methods and control ports supported by
PCIE_F1
About this manual
Copyright Statement
The copyright of this document belongs to Loongson Technology Corporation Limited. Without written permission, no company or individualmay disclose, reproduce or otherwise distribute any part of this document to third parties. Otherwise, they will be held legally responsible.
Disclaimer
This document provides only periodic information, and the contents contained may be updated at any time without notice, depending on the actual situation of the product. Loongson Technology Corporation Limited is not responsible for any direct or indirect damage aused by the improper use of the document.
Loongson Technology Corporation Limited
Building No.2, Loongson Industrial Park,
Zhongguancun Environmental Protection Park, Haidian District, Beijing
Tel: 010-62546668
Fax: 010-62600826
Reading Guide
This manual describes the overall bridge architecture, clock structure, address space, configuration registers, and individual functional interfaces, primarily for BIOS and kernel developers.
Translator’s Note
These documents were translated by Yanteng Si and Feiyang Chen.
This is the translation of https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-v2.00-CN.pdf.
Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in this document, please feel free to correct.
License
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
Contributors
Since the release of the project, we have gotten several errata and content changes donated. Here are all the people who have contributed to LoongArch Documentation as an open source project. Thank you everyone for helping make this a better book for everyone.
The contributors are listed in alphabetical order.
Chao LI <lichao@loongson.cn>
Chenghua Xu <xuchenghua@loongson.cn>
Dandan Zhang <zhangdandan@loongson.cn>
Feiyang Chen <chenfeiyang@loongson.cn>
FreeFlyingSheep <fyang.168.hi@163.com>
Konstantin Romanov <konstantinsromanov@gmail.com>
LI Chao <lichao@loongson.cn>
limeidan <limeidan@loongson.cn>
liuzhensong <liuzhensong@loongson.cn>
mengqinggang <mengqinggang@loongson.cn>
Qi Hu <huqi@loongson.cn>
qmuntal <quimmuntal@gmail.com>
tangxiaolin <tangxiaolin@loongson.cn>
WANG Xuerui <git@xen0n.name>
wangguofeng <wangguofeng@loongson.cn>
Wu Xiaotian <wuxiaotian@loongson.cn>
Wu Xiaotian <yetist@gmail.com>
Xi Ruoyao <xry111@mengyan1223.wang>
Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
Yang Yujie <yangyujie@loongson.cn>
Yanteng <siyanteng@loongson.cn>
Yanteng Si <siyanteng@loongson.cn>1. Introduction
1.1. Introduction to this Manual
1.1.1. Contents of the Chapters
Section 1 is an introduction that provides an overview of the features and functions of this bridge chip.
Section 2 introduces the bridge chip clock structure, describes the clock of the bridge chip, and details the clock-related hardware configuration and software usage.
Section 3 introduces the address space of the bridge chip, describing the entire address space of the processor (Loongson 3 processor) + bridge chip and the address space distribution inside the bridge chip.
Section 4 introduces the bridge chip configuration registers.
Section 5 introduces interrupts.
Section 6 describes the HPET controller.
Section 7 introduces the HT controller.
Sections 8-14 describe the low-speed interface and other internal functions of the bridge chip. These include: address space description, UART serial controller, I2C controller, PWM controller, and other internal functions. I2C controller, PWM controller, ACPI power management module, real-time clock RTC, and GPIO interface.
Section 15 describes the GMAC controller.
Section 16 describes the USB controller, including the EHCI controller and the OHCI controller.
Section 17 describes the Graphics Processing Unit GPU.
Section 18 describes the display controller DC.
Section 19 describes the HDA controller.
Section 20 describes the AC97 controller.
Section 21 describes the SATA controller.
Section 22 describes the PCIE controller.
Section 23 introduces the SPI controller.
Section 24 introduces the LPC controller.
Appendix 1 explains the chip pin multiplexing relationship.
Appendix 2 gives the software usage notes.
1.1.2. Conventions of this Manual
Note: The bit field of Reserved in the register description in the text is either a read-only attribute or a read-write attribute. Regardless of the attribute of the bit field, the software must ensure that the value of the bit field is not changed, that is, if the software needs to modify a register containing a Reserved bit field, it must ensure that the value written to the Reserved bit field is the same as the value read from the bit field.
For ease of presentation, the following abbreviations are used to denote the register attributes.
RO Read-only
WO Write-only
R/W Read-Write
R/WC read-write, write clear
1.2. Overview of the Bridge
The Loongson 7A1000 bridge chip (hereafter referred to as the bridge chip) is Loongson’s first dedicated chipset product, providing north-south bridge functionality for Loongson processors. The bridge chip is connected to the Loongson Series 3 processor via the HT high-speed bus interface and has an integrated GPU, DisplayController, DDR3 SDRAM memory controller, and PCIE, SATA, USB, GMAC, I2C, UART, GPIO, and other interfaces.
Main Characteristics of the Bridge Piece
-
16-bit HT 3.0 interface
-
Support dual-way bridge chip mode
-
2D/3D GPU
-
Display controller, supports dual DVO display
-
16-bit DDR3 graphics memory controller
-
3 x8 PCIE 2.0 interfaces, each x8 interface can be split into 2 independent x4 interfaces
-
2 x4 PCIE 2.0 interfaces that can be split into 6 independent x1 interfaces
-
3 SATA 2.0 ports
-
6 USB 2.0 ports
-
2 RGMII Gigabit LAN interfaces
-
HDA/AC97 configurable interface
-
RTC support
-
HPET support
-
UART interface
-
I2C interface
-
LPC interface
-
SPI interface
-
GPIO interface
-
Support ACPI specification
-
Support JTAG bound scan
1.3. Main Functions of the Bridge
HT Interface
The bridge is connected to the processor via the HT interface, which is compatible with HT3.0 protocol and supports 200/400/800/1600Mhz interface frequency and 8/16-bit interface width. In addition to being used as a single bridge chip, it can also be configured as a dual bridge chip mode to support direct data transfer with both processors.
Graphics Processing
The GPU supports OpenGL ES 2.0 and OpenGL ES 1.1; OpenVG, Futuremark certified, BitBLT and Stretch BLT, rectangle fill, hardware line drawing, color font rendering, YUV color space conversion, and high quality scaling. Space conversion, high quality scaling, etc. The display controller supports dual DVO signal output and hardware cursor, gamma correction, output dithering, etc. The memory interface uses 16-bit DDR3 SDRAM interface with a maximum data rate of 1333 Mbps.
PCIE Interface
The PCIE 2.0 protocol-compliant interface contains a total of 32 data links supporting up to 5G b/s in each data direction (10G b/s in both directions) and a total of 12 PCIE controllers. 32 data links can be divided into 3 x8 interfaces and 2 x4 interfaces; each x8 interface can be configured as 2 x4 interfaces. Each x8 interface can be configured as two x4 interfaces independently; of the two x4 interfaces, one can be configured as four x1 interfaces independently, and the other as two x1 interfaces independently.
SATA Controllers
Integrated 3 SATA host controllers, each controlling 1 SATA interface, each supporting up to 3 Gb/s data rate and compatible with SATA 2.6 protocol. SATA controllers are compatible with AHCI 1.1 specification.
USB Controllers
Two USB controllers control six independent USB host interfaces, supporting up to USB 2.0 protocol with maximum transfer speeds of up to The two USB controllers control six independent USB host interfaces, supporting up to USB 2.0 protocol and transfer speeds up to 480 Mbps, and are compatible with USB 1.1 full-speed and low-speed transfers.
GMAC Controller
Integrated two 10/100/1000Mbps adaptive Ethernet MAC controllers, compatible with IEEE 802.3, connect external GMAC PHY chip through RGMII interface, half-duplex/full-duplex adaptive, support Timestamp function, support network wake-up.
HDA Controller
Supports 16, 18 and 20-bit sampling accuracy, variable rate, sampling rate up to 192KHz, 7.1 channel surround sound output, and three audio inputs.
SPI Controller
Integrated SPI host controller, supports standard read, sequential address read, fast read, dual I/O and other read modes.
UART
Integrated 1 full-featured UART controller, full-duplex asynchronous data receive/transmit, 16-bit programmable clock counter, support receive timeout detection, configurable as 4 two-wire serial ports (TXD/RXD).
I2C Bus
Compatible with I2C standard, operates in master device mode, supports 7-bit addressing and 10-bit addressing modes.
PWM
Four PWM outputs with internal 32-bit counter, supporting pulse generation and detection.
HPET
Compatible with HPET specification, supports 64-bit counter timestamp function, 32-bit timer, 1 periodic interrupt and Supports 1 periodic interrupt and 2 non-periodic interrupts.
RTC
Timing accurate to 0.1 second, can generate 3 timing interrupts, supports timed power-on function.
Interrupt Controller
Internal integrated interrupt controller supports up to 64 interrupt sources, dual interrupt outputs, software set interrupts, configurable trigger mode, and intelligent interrupt distribution.
ACPI Power Management
Supports clock gating, PHY shutdown, USB/GMAC wake-up, and auto-start for incoming calls.
GPIO
1 dedicated GPIO pin, 56 multiplexed GPIO pins, support input interrupt function.
1.4. Structure of the Bridge
2. Bridge and System Clock
2.1. Bridge Clock
The bridge requires a 100Mhz clock and a 32.768 K crystal as reference clock input (and a 33Mhz clock input if using the LPC bus)
| Clock | Frequency | Description |
|---|---|---|
|
|
|
|
|
Reserved |
|
|
LPC |
|
|
HT |
|
|
PCIE_F0 |
|
|
PCIE_F1 |
|
|
PCIE_H |
|
|
PCIE_G0 |
|
|
PCIE_G1 |
|
|
SATA0 |
|
|
SATA1 |
|
|
SATA2 |
|
|
Reserved |
|
|
12Mhz crystal input |
Note: Input clocks not provided need to be grounded through a 10Kohm resistor.
| Clock | Frequency | Description |
|---|---|---|
|
|
33.3Mhz single-ended clock output. Can be used as a memory reference clock for the Loongson 3 processor. |
|
|
|
|
|
|
|
|
Variable frequency single-ended clock output. Default is |
Note: 1. The CLKO`UT25M and CLKOUTFLEX pins can be multiplexed as GPIO functions.
2.2. Clock-related Configuration Pins
The bridge chip sets a number of pins to set the bridge clock generation method, these configuration pins are mainly used as a backup design, the normal motherboard design does not need to change the value of these configuration pins except for CLKSEL[7:6] (dangling or kept as default values). Bridge clock-related configuration pins are shown in the following table:
| Pin | Direction | Default Value | Description |
|---|---|---|---|
|
|
|
Reserved |
|
|
|
Reserved |
|
|
|
Reserved |
|
|
|
HT PHY reference clock selection.
|
|
|
|
HT frequency configuration mode (recommended setting is 0: The HT clock is configured in software mode. If the PLL frequency of the HT is not modified using software, the HT bus frequency remains fixed (HT1.0 mode: 1: The HT clock can only be used in hardware configuration mode. In this case, software modification of the HT PLL frequency is not valid, and only a few frequencies can be selected via registers. For |
|
|
|
Reserved |
2.3. Description of Clock Function
The bridge contains multiple PLLs and clock divider modules to generate the individual clocks needed for the bridge.
The bridge contains 5 PLLs, each of which can provide up to 3 clock outputs. The five PLLs are used for the following purposes
-
A device PLL to generate the clocks for USB/SATA, GMAC.
-
A graphics PLL to generate clocks for GPU, DC, and graphics memory.
-
One system PLL to generate clocks for the internal bus, HDA bitclk, flex clkout.
-
Two PIX PLLs for generating two independent pixel clocks to support dual independent displays.
2.4. Description of PLL Function
The output clock frequency is calculated as follows.
clock_out = refclk / div_ref * loopc / divoutN
The refclk of 7A is fixed at 100MHz, and the output of the input divider (refclk / div_ref) needs to be guaranteed to be in the range of 20 In addition, it is necessary to ensure that the output of the input divider (refclk / div_ref) is in the range of 20 - 40MHz, and the frequency after frequency doubling module (refclk / div_ref * loopc) is in the range of 1.2GHz - 3.2GHz.
The PLL-related configuration signals and their descriptions are shown in the follow table. The locations of these configuration signals are shown in Section 4 Bridge Configuration Registers.
| Signal | Digit | Direction | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
RO |
|
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
R/W |
Set |
|
|
R/W |
|
|
|
R/W |
|
2.5. Configuration Method of PLL
When SYS_CLKSEL[1:0] is 00b, it means the output frequency of PLL can be changed by software. In this configuration, the default clock frequency at bridge startup is the external reference clock frequency, and software configuration of the bridge clock is required during processor startup. The process of modifying the clock configuration through software is as follows:
-
set
sel_pll_out*to0. -
set the
pll_pdsignal to1. -
set
set_pll_paramto0. -
set the value of
pll_div_ref/pll_loopc/pll_div_out*. -
set
set_pll_paramto1. -
set the
pll_pdsignal to0. -
wait for the PLL lock signal
pll_lockedto change to1. -
set
sel_pll_out*to1.
3. Address Space
3.1. Overview of Loongson 3 and Loongson 7A Address Space
As a bridge for the HT interface, the bridge supports a 40-bit address space internally. Without the SWIOTLB, the Loongson3 processor + bridge supports a maximum of 1TB of memory address space. To support multi-processor systems, we use a few bits (up to 4 bits) of the bridge chip’s internal address as the destination node number for the bridge chip’s internal device DMA access. This means that the bridge chip can support a processor system with up to 16 nodes. Considering that in practice Loongson uses systems with up to 4 nodes Therefore, this section describes the maximum number of nodes supported. For a 4-node system, the address space size for a single processor node is 256GB.
From the CPU’s perspective - that is, the device address space accessible to the CPU - the address space of a bridge chip consists of three parts: configuration space, PCI I/O space, and PCI MEM space. The address space of a bridge chip has the same form as the address space defined by PCI.
-
Configuration space: this address space is used to access the configuration headers of the devices inside the bridge chip (including devices extended through the PCIE bus), and its address composition conforms to the address organization form of PCI configuration access.
-
I/O space: This address space is used to access the I/O address space defined by the PCI protocol. Only PCIE has this address space in the bridge chip for accessing downstream devices of the PCIE controller through I/O type requests.
-
MEM space: All address spaces other than the above two address spaces are MEM spaces.
The bridge chip’s configuration space corresponds to the HT bus configuration space of the HT bus, with a size of 32MB. the bridge chip’s PCI I/O space corresponds to the HT bus I/O space, with a size of 32MB. the bridge chip’s PCI MEM space corresponds to the HT bus MEM space, with a size of 1012GB. the PCI MEM space is used to The PCI MEM space is used to access the MEM space of the bridge’s internal PCIE devices, the MEM and IO space of devices other than PCIE devices, and the bridge’s configuration register space.
The latter two address spaces (PCI I/O space and PCI MEM space) are part of the overall processor address space. and the system software can assign them to any location from 0 - 1TB*. When the software accesses them, it needs to map them into HT1’s address space segment via the processor’s level 1 XBAR or directly add HT1’s address space offset to that access address.
Note*: Except for the address segment 0x0f000000-0x0fffffff. This address segment cannot be used as a bridge device address space.
From the perspective of DMA accesses - that is, accesses to the address space initiated by the bridge chip’s internal devices - the address space available includes the processor’s memory space and the bridge chip’s memory space. The size of the processor’s memory space varies depending on the number of nodes in the system, and the total DMA address space is 1 TB. For a 4-node system, the DMA address space must be located within the lower 256 GB of the node address space so that the bridge can directly access the memory of up to 4 nodes. Devices within the bridge chip that can initiate DMA operations include: GPU, DC, PCIE, USB, SATA, GMAC, HDA, and AC97.
Both types of addresses (the bridge’s address space and the processor’s address space) are addressed in a uniform manner, i.e., the processor’s memory space, the processor’s configuration space, the bridge’s configuration access space, the I/O space, and the MEM space, are all located in the same address space and do not overlap with each other. For a single node system, this address space has a maximum size of 1TB.
The access addresses of the devices inside the bridge chip (PCI I/O space and PCI MEM space) are designed to be software configurable to support device discovery and management for the PCI architecture. Each device (device block) inside the bridge contains a PCI configuration header. The software accesses the configuration header to obtain information about the type of the device, the size of the address space supported, etc., and sets the address space of the device by configuring the device’s BAR register. This approach is consistent with the 780E.
The following is an example of a Loongson 3A+ bridge chip system to illustrate the address space allocation for the entire computer system. one way of dividing the address space for the 3A+ bridge chip is shown in the following figure.
Note: The address in the figure is the low address, not including the node number and high address.
In the address space allocation method in the figure above, the
0x0000,0000 - 0x0fff,ffff is the low 256MB memory space of the system.
0x1000,0000 - 0x17ff,fff is the fixed device address space of the bridge, which includes interrupt controller, HPET, confbus, MISC low-speed devices, and LPC. ,ffff (HT1’s MEM space)
0x1800,0000 - 0x19ff,ffff is the PCI I/O space of the bridge chip, the software can allocate the I/O space of the PCIE devices in the bridge chip to this address space, which is mapped to 0xefd,fc00,0000 - 0xefd,fdff through the configuration window of the first-level XBAR, ffff (I/O space of HT1).
0x1a00,0000 - 0x1bff,ffff is the configuration space of the bridge chip, which is used to access the configuration header of the internal device of the bridge chip, and the access method is compatible with the PCI protocol, the bit[23:8] of the address bit corresponds to the bus number, device number and func number in order, and this address is mapped to 0xefd, fe00,0000 - 0xefd,fff,fff (HT1’s bus configuration space).
0x1c00,0000 - 0x1dff,ffff is the LPC MEM address space of 3A.
0x1f00,0000 - 0x1fff,ffff is the 3A’s LPC device space.
0x2000,0000 - 0x2fff,ffff is the reserved space for the processor.
0x3000,0000 - 0x3fff,ffff is the configuration space for 3A.
0x4000,0000 - 0x7fff,ffff is the PCI MEM space of the bridge chip. This address is mapped to 0xe00,4000,0000 - 0xe00,7fff,fff (the MEM space of HT1) through the configuration window of level 1 XBAR.
0x8000,0000 - MEM_UP_LIMIT is the high memory address space of 3A.
MEM_UP_LIMIT - 0xfc,ffff,ffff is the PCI MEM space of the bridge. This address is mapped to 0xe00,0000,0000+MEM_UP_LIMIT - 0xefc,ffff,ffff (the MEM space of HT1) through the configuration window of Level 1 XBAR.
3.2. PCI Devices and Functions
Devices with DMA capability inside the bridge and some other devices contain a standard PCI configuration header. The devices that contain PCI configuration headers include: GPU, DC, PCIE, USB, SATA, GMAC, HDA/AC97, LPC, and SPI. the bus number, device number, and function number of each device are listed in the following table
| Bus: Device: Function | Function Description |
|---|---|
Bus 0:Device 0:Function 0 |
HT lo |
Bus 0:Device 1:Function 0 |
HT hi |
Bus 0:Device 3:Function 0 |
GMAC0 |
Bus 0:Device 3:Function 1 |
GMAC1 |
Bus 0:Device 4:Function 0 |
USB0 OHCI |
Bus 0:Device 4:Function 1 |
USB0 EHCI |
Bus 0:Device 5:Function 0 |
USB1 OHCI |
Bus 0:Device 5:Function 1 |
USB1 EHCI |
Bus 0:Device 6:Function 0 |
GPU |
Bus 0:Device 6:Function 1 |
DC |
Bus 0:Device 7:Function 0 |
HDA1 |
Bus 0:Device 7:Function 1 |
AC971 |
Bus 0:Device 8:Function 0 |
SATA0 |
Bus 0:Device 8:Function 1 |
SATA1 |
Bus 0:Device 8:Function 2 |
SATA2 |
Bus 0:Device 9:Function 0 |
PCIE_F0 Port02 |
Bus 0:Device 10:Function 0 |
PCIE_F0 Port12 |
Bus 0:Device 11:Function 0 |
PCIE_F0 Port22 |
Bus 0:Device 12:Function 0 |
PCIE_F0 Port32 |
Bus 0:Device 13:Function 0 |
PCIE_F1 Port03 |
Bus 0:Device 14:Function 0 |
PCIE_F1 Port13 |
Bus 0:Device 15:Function 0 |
PCIE_G0 port04 |
Bus 0:Device 16:Function 0 |
PCIE_G0 port14 |
Bus 0:Device 17:Function 0 |
PCIE_G1 port05 |
Bus 0:Device 18:Function 0 |
PCIE_G1 port15 |
Bus 0:Device 19:Function 0 |
PCIE_H port06 |
Bus 0:Device 20:Function 0 |
PCIE_H port16 |
Bus 0:Device 22:Function 0 |
SPI |
Bus 0:Device 23:Function 0 |
LPC7 |
Notes.
-
when hda_sel is 1, HDA controller can be discovered; when hda_sel is 0, AC97 controller can be discovered.
-
When PCIE_F0 works in x4 mode, only Port 0 is visible, Port 1-3 is not visible; when PCIE_F0 works in non-x4 mode, Port 0-3 is visible. When PCIE_F0 works in non-x4 mode, Port 0-3 is visible. 3.
-
When PCIE_F1 is operating in x4 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_F1 is operating in non-x4 mode, Port 0-1 is visible. When PCIE_F1 is operating in non-x4 mode, Port 0-1 is visible. 4.
-
When PCIE_G0 is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_G0 is operating in x4 mode, Port 0-1 is visible. mode, Port 0-1 is visible. 5.
-
When PCIE_G1 is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_G1 is operating in x4 mode, Port 0-1 is visible. When PCIE_G1 is operating in x4 mode, Port 0-1 is visible. 6.
-
When PCIE_H is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_H is operating in x4 mode, Port 0-1 is visible.
-
LPC(D23:F0) is only visible when LPC module is enabled.
When the bus number, device number, function number and address offset accessed by the configuration header are invalid, the write operation is invalid; the data obtained by the read operation is 0xFFFFFFFF.
3.3. Access Address of the PCI Configuration
The processor can access the configuration space of the bridge chip through two address spaces. One is the standard configuration access space defined by HT (0xFD_FE00_0000 - 0xFD_FFFF_FFFF) and the other is the reserved address space of HT (0xFE_0000_0000 - 0xFE_1FFF_FFFF). The configuration space size for each bridge device accessed through the HT standard configuration access space is 256 bytes; the configuration space size for each bridge device accessed through the reserved address space is 4K bytes.
The maximum configuration space size per device is 256 bytes when using the HT-defined standard configuration access space (0xFD_FE00_0000-0xFD_FFFF_FFFF) to access the bridge slice. The address [39:24] determines the configuration header type (0xFDFE is Type0, 0xFDFF is Type1); [23:16] indicates the Bus Number; [15:11] indicates the Device Number; [10:8] indicates the Function Number; [7:0] indicates the offset. The following diagram shows the meaning of the address segment for the CPU to access the PCI configuration space using the HT standard configuration access space
When using the HT’s reserved address space (0xFE_0000_0000 - 0xFE_1FFF_FFFF) to access bridge slices, the maximum configuration space size per device is 4K bytes. The address [39:28] determines the configuration header type (0xFE0 is Type0, 0xFE1 is Type1); [23:16] indicates the Bus Number; [15:11] indicates the Device Number; [10:8] indicates the Function Number; [27:24] and [7:0] are combined to represent the offset. The following diagram illustrates the meaning of the address segment for the CPU to access the PCI configuration space using the HT reserved address space.
In general, it is recommended to use the HT standard configuration access space (0xFD_FE00_0000-0xFD_FFFF_FFFF) for PCI configuration header access.
3.4. Example of Bridge Device Address Space Allocation
Access to the bridge chip devices is mainly done through the PCI MEM space. The software can assign any access address for each device on the bridge chip within this address segment. The internal PCI devices of the bridge chip include: GPU/DC, GMEM, PCIE, USB, SATA, GMAC, HDA/AC97, LPC, SPI, all of which can be seen through lspci. The access addresses of these devices (except LPC) can be dynamically assigned by software. One way of allocation is as follows: by scanning the PCI bus and reading the configuration space of each device (PCI mode orientation) to get the size of MEM space and I/O space used by each device, the system software allocates the appropriate size of MEM space from the address 0x40000,0000-0x7fff,fff, and from 0x1800, 0000-0x19ff,ffff. The system software allocates the appropriate size of I/O space (PCIE devices) from 0x40000,0000-0x7fff,ffff.
In addition to these PCI type devices, the bridge also contains some devices that are accessed using fixed addresses, such as: interrupt controllers, HPET controllers, confbus In addition to these PCI-type devices, the bridge also contains devices that are accessed using fixed addresses, such as: interrupt controllers, HPET controllers, confbus configuration registers, MISC low-speed device blocks, and LPCs.
The following two tables give an example of an address allocation for a bridge chip fixed address device and a PCI device, along with their address space size and supported access types. For the access types, B indicates byte access (1byte), H indicates half-word access (2byte), W indicates word access (4byte), D indicates double-word access (8byte), Q indicates 4-word access (16byte), and C indicates cacheline access.
| Module | Address space | Address space size | Access type |
|---|---|---|---|
|
|
|
BHW |
|
|
|
BW |
|
|
|
BHW |
|
|
|
BW |
|
|
|
W |
|
|
|
BHWDQC |
|
|
|
B |
|
|
|
B |
| Module | Address space | Address space size | Access type |
|---|---|---|---|
|
|
|
W |
|
|
|
W |
|
|
|
BHWDQC |
|
|
|
BHW |
|
|
|
BHW |
|
|
|
BHWDQC |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
W |
|
|
|
BHW |
|
|
|
W |
|
|
|
B |
The size of the address space of the above devices is fixed, except for PCIE MEM and Graphic Memory, which can be changed by software.
The BIOS needs to modify the MASK value of the BAR register 2/3 of the GPU configuration header by accessing the bridge configuration register GMEM_BAR_MASK to configure the size of Graphic Memory. Graphic Memory size, and then the software will get the graphic memory size through PCI The software then scans through the PCI to obtain the size of the graphics memory.
In the case of using a PCIE external discrete graphics card, the discrete graphics memory space that comes with the discrete graphics card is located in the PCIE MEM address space and is managed as a PCIE device.
4. Bridge Configuration Register
The bridge chip sets up registers to configure certain features of the bridge chip that are not specific to a particular interface (PCIE, USB, etc.). These registers are arranged uniformly in the bridge’s configuration register space (not the PCI configuration access space). The address space size of the bridge configuration registers is 64KB, and the starting address (internal space of the bridge) is configured by the BIOS.
The bridge chip configuration registers contain the following.
-
Bridge chip general configuration (
0x0-0x47f). -
PLL configuration (0x480 - 0x4cf).
-
PCIE controller and PHY configuration (
0x580-0x617). -
SATA controller and PHY configuration (
0x740-0x76f). -
Memory capacity configuration registers (
0x3838-0x383f). -
Bridge ID (0x3ff8 - 0x3fff).
| Address Offset | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
General Configuration Register |
|
|
R/W |
General Configuration Register |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
Device Frequency Division Configuration |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
Configuration of |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
RO |
|
4.1. HT clock enable and DMA routing configuration
Offset Address: 0418-041Bh
Attribute: R/W
Default value: 3h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
HT Controller
|
Offset Address: 041C-041Fh
Attribute: R/W
Default value: 000a_a800h
Size: 32 bits
This register is used to configure the routing information for the device’s DMA accesses (i.e., the destination processor for the DMA access and the HT controller through which it passes).
Since the HT bus only supports 40-bit addresses and the processor space (and the DMA access space) supports 64-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports:
-
the bridge chip stores the node number information in a certain number of bits of the HT bus address;
-
on the processor side, the node information is remapped to the processor’s node bit field using the address translation function of the HT receive window.
The LS7A1000 implements the DMA access node number translation function, which allows the node number in the 64-bit address space issued by the device to be automatically mapped to the HT address space by configuring this register.
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
Address Offset of the mapped
…
This register determines the maximum address range for |
|
|
R/W |
The address offset (relative to |
|
|
R/W |
Reserved |
|
|
R/W |
Node number mask for
|
4.2. General Configuration Register 0
Offset Address: 0420-0423h
Attribute: R/W
Default value: CCCC_3CE0h
Size: 32 bits
This register contains configuration information related to PCIE, graphics processing unit (GPU, display controller, graphics memory).
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enables the port1 clock for
|
|
|
R/W |
Enables the port0 clock for
|
|
|
R/W |
Enable
|
|
|
R/W |
Software reset of
|
|
|
R/W |
Enables the port1 clock for
|
|
|
R/W |
Enables the port0 clock for
|
|
|
R/W |
Enable
|
|
|
R/W |
Software reset of
|
|
|
R/W |
Enables the port1 clock for
|
|
|
R/W |
Enables the port0 clock for
|
|
|
R/W |
Enable
|
|
|
R/W |
Software reset of
|
|
|
R/W |
Enables the port1 clock for
|
|
|
R/W |
Enables the port0 clock for
|
|
|
R/W |
Enable
|
|
|
R/W |
Software reset of
|
|
|
R/W |
Reserved |
|
|
R/W |
Enables the port3 clock for
|
|
|
R/W |
Enables the port2 clock for
|
|
|
R/W |
Enables the port1 clock for
|
|
|
R/W |
Enables the port0 clock for
|
|
|
R/W |
Enable
|
|
|
R/W |
Software reset of
|
|
|
R/W |
Enables clocking of dc
|
|
|
R/W |
Enable the clock of the gpu
|
|
|
R/W |
Enables the clock for gmem
|
|
|
R/W |
Reserved |
|
|
R/W |
Clock selection for pcie.
If fix_pcie_clksel is |
|
|
R/W |
Reserved |
|
|
R/W |
Read/Writeing PCIE, graphics devices using fixed addresses.
If fix_default_route is |
Offset Address: 0424-0427h
Attribute: R/W, RO
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
Disable access to the
|
|
|
R/W |
Reserved |
|
|
RO |
|
|
|
RO |
pcie_g1 port 0 clock ready
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
GPU/DC uncache access acceleration can be
|
4.3. General Configuration Register 1
Offset Address: 0430-0433h
Attribute: R/W
Default value: 00F9_BBF2h
Size: 32 bits
This register contains configuration information related to USB, SATA, GMAC, HDA/AC97, LPC, and SPI.
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
`1: Access acceleration on |
|
|
R/W |
Configuration register
|
|
|
R/W |
Low-speed misc device uncache acceleration enable
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
sata
|
|
|
R/W |
usb
|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
Enables usb EHCI
|
|
|
R/W |
Use fixed addresses to access devices such as
If fix_default_route is |
Note: In order to support the USB sleep-wake function, the USB reference clock must use a 12MHz external crystal.
Offset Address: 0430-0437h
Attribute: R/W
Default value: 1209_9900h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enables
|
|
|
R/W |
RTC crystal oscillator restart |
|
|
R/W |
RTC Crystal Oscillator Driver Configuration |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
`1: Hold reset |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
4.4. Pin Multiplexing Configuration Register
Offset Address: 0440-0443h
Attribute: R/W
Default value: FFFF_FFFFh
Size: 32 bits
This register contains configuration information related to pin multiplexing.
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
UART operating mode selection for pin UART_DTR/DSR (when selected as UART mode)
|
|
|
R/W |
UART operating mode selection for pin UART_RTS/CTS (when selected as UART mode)
|
|
|
R/W |
UART operating mode selection for pin UART_TXD/RXD (when UART mode is selected)
When bit[31:29] is not equal to 0, regardless of the value of this bit, UART_TXD/RXD operates in two-wire UART mode regardless of the value of the bit. |
|
|
R/W |
Operating mode selection for pin CLKOUTFLEX
|
|
|
R/W |
Operating mode selection for pin CLKOUT25M
|
|
|
R/W |
Operating mode selection for LPC pins (LPC_AD0-3/LPC_SERIRQ/LPC_FRAMEn)
|
|
|
R/W |
Operating mode selection for pin UART_DTR/DSR (determined together with bit20) [bit24, bit20]. 00b: working in GPIO mode x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode) 10b: working in I2C mode |
|
|
R/W |
Operating mode selection for pin UART_RI/DCD (determined together with bit19) [bit23, bit19]. 00b: working in GPIO mode x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode) 10b: working in I2C mode |
|
|
R/W |
Operating mode selection for pin UART_TXD/RXD
|
|
|
R/W |
Operating mode selection for pin UART_RTS/CTS
|
|
|
R/W |
Operating mode selection for pin UART_DTR/DSR (determined together with bit24) [bit24, bit20]. 00b: working in GPIO mode x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode) 10b: working in I2C mode |
|
|
R/W |
Operating mode selection for pin UART_RI/DCD (determined together with bit23) [bit23, bit19]. 00b: working in GPIO mode x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode) 10b: working in I2C mode |
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin USB_OC1
|
|
|
R/W |
Operating mode selection for pin USB_OC0
|
|
|
R/W |
Operating mode selection for pin SATA2_LEDn
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for
For pins
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating mode selection for pin
|
|
|
R/W |
Operating Mode Selection for Pin
|
|
|
R/W |
Operating mode selection for pin
|
The multiplexing relationship between the VSB_GATEn pin and GPIO01 is configured by the internal register (PMCON_RESUME) of the power management module, see 12.3 Register Description.
See the chip pin multiplexing table in Appendix 1 for a cross-reference to the chip pin multiplexing table.
4.5. PLL0 Configuration Register
Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL. This register is used to set PLL0, where output clock 1 is used to generate the 125MHz clock required by the GMAC, and output clock 0
is used to generate the controller clock for USB/SATA.
Offset Address: 0480-0483h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
This register contains configuration information related to pin multiplexing.
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Offset Address: 0484-0487h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL powerdown |
|
|
R/W |
PLL internal bypass |
|
|
R/W |
Set |
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
RO |
|
|
|
R/W |
|
4.6. PLL1 Configuration Register
Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL.
This register is used to set PLL1, where output clock 2 is used to generate the GPU clock, output clock 1 is used to generate the GMEM clock, and output clock 0 is used to generate the DC clock.
Offset Address: 0490-0493h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Offset Address: 0494-0497h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
Set |
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
R/W |
Select |
|
|
RO |
|
|
|
R/W |
|
4.7. PLL2 Configuration Register
Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL. This register is used to set PLL2, where output clock 2 is used to generate the CLKOUTFLEX clock, output clock 1 is used to generate the internal bus clock, and output clock 0 is used to generate the 24MHz bitclk clock required by the HDA.
Output Clock 1 is used to generate the internal bus clock, and Output Clock 0 is used to generate the 24MHz bitclk clock required by the HDA.
Address Offset: 04A0-04A3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL Multiplier |
|
|
R/W |
PLL output clock |
|
|
R/W |
PLL output clock |
|
|
R/W |
PLL output clock |
Address Offset: 04A4-04A7h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL powerdown |
|
|
R/W |
PLL internal bypass |
|
|
R/W |
Set PLL configuration parameters |
|
|
R/W |
Select PLL output clock |
|
|
R/W |
Select PLL output clock |
|
|
R/W |
Select PLL Output Clock |
|
|
RO |
PLL Lock |
|
|
R/W |
PLL Input Frequency Division Number |
4.8. PLL_PIX_0 Configuration Register
Refer to Section 2.5 PLL Configuration Methods for the specific usage of the PLL.
This register is used to set PLL_PIX_0, where output clock 0 is used to generate the PIX0 clock.
Address Offset: 04B0-04B3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL Multiplier |
|
|
R/W |
Reserved |
|
|
R/W |
PLL Output Clock |
Address Offset: 04B4-04B7h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL powerdown |
|
|
R/W |
PLL internal bypass |
|
|
R/W |
Set PLL configuration parameters |
|
|
R/W |
Reserved |
|
|
R/W |
Select PLL output clock |
|
|
RO |
PLL Lock |
|
|
R/W |
Number of PLL input divisions |
4.9. PLL_PIX_1 Configuration Register
Refer to Section 2.5 PLL Configuration Methods for the specific usage of the PLL. This register is used to set PLL_PIX_1, where output clock 0 is used to generate the PIX1 clock.
Address Offset: 04C0-04C3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL Multiplier |
|
|
R/W |
Reserved |
|
|
R/W |
PLL Output Clock 0 Divider |
Address Offset: 04C4-04C7h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PLL powerdown |
|
|
R/W |
PLL internal bypass |
|
|
R/W |
Set PLL configuration parameters |
|
|
R/W |
Reserved |
|
|
R/W |
Select PLL output clock |
|
|
RO |
PLL lockout |
|
|
R/W |
Number of PLL input divisions |
4.10. PCIE_F0 PHY Configuration Register
This set of registers contains the control signals for PCIE_F0 PHY.
Address Offset: 0588-058Bh
Attribute: R/W,RO
Default value: 0006_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enable software to configure the operating mode of PCIE_F0 0: the operating mode is determined by the hardware pin 1: The operating mode is determined by the software configuration (bit26) |
|
|
R/W |
Software configuration of PCIE_F0 operating modes 0: working in x1 mode 1: working in x4 mode |
|
|
R/W |
Set PHY into low-power mode |
4.11. PCIE_F0 PHY Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_F0 PHY internal control register. This register controls the 4 data links of PCIE_F0.
Address Offset: 0590-0593h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data.In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register. |
|
|
R/W |
PHY configures the address. |
Address Offset: 0594-0597h
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
PHY One access completion indicates the completion of reading and writing to PHY. Write completion indicates that the write data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register |
|
|
R/W |
0 - Read and write to this set of registers will trigger PHY configuration access operation 1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write |
|
|
R/W |
Start a read operation or a write operation. 0: Read operation 1: Write operation |
4.12. PCIE_F1 PHY Configuration Register
This set of registers contains the control signals for PCIE_F1 PHY.
Address Offset: 05A8-05ABh
Attribute: R/W,RO
Default value: 0006_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enable software to configure the operating mode of
|
|
|
R/W |
Software configuration of PCIE_F1 operating modes
|
|
|
R/W |
Set |
4.13. PCIE_F1 PHY Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_F1 PHY internal control register. This register controls the 4 data links of PCIE_F1.
Address Offset: 05B0-05B3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY configuration address |
Address Offset: 05B4-05B7h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
RO |
|
|
|
R/W |
The completion of one access to |
|
|
R/W |
|
|
|
R/W |
Start a read operation or a write operation.
|
4.14. PCIE_H PHY Configuration Register
This group of registers contains the control signals for PCIE_H PHY.
Address Offset: 05C8-05CBh
Attribute: R/W,RO
Default value: 0006_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enable software to configure the operating mode of
|
|
|
R/W |
Software configuration of
|
|
|
R/W |
Set the high four bits of |
|
|
R/W |
Set |
4.15. PCIE_H PHY LO Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_H PHY LO internal control register. This register controls the the lower 4 data links (lane0-3) of PCIE_H.
Address Offset: 05D0-05D3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 05D4-05D7h
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register |
|
|
R/W |
0 - Read or write to this group of registers will trigger the PHY configuration access operation 1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write |
|
|
R/W |
Start a read operation or a write operation. 0: Read operation 1: Write operation |
4.16. PCIE_H PHY HI Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_H PHY HI internal control register. This register controls the the high 4 data links (lane4-7) of PCIE_H.
Address Offset: 05D8-05DBh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configures the read and write data. In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 05DC-05DFh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register |
|
|
R/W |
0 - Read or write to this group of registers will trigger the PHY configuration access operation 1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write |
|
|
R/W |
Start a read operation or a write operation. 0: Read operation 1: Write operation |
4.17. PCIE_G0 PHY Configuration Register
This set of registers contains the control signals for PCIE_G0 PHY.
Address Offset: 05E8-05EBh
Attribute: R/W,RO
Default value: 0006_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Enables software to configure the operating mode of PCIE_G0 0: the operating mode is determined by the hardware pins 1: The operating mode is determined by the software configuration (bit26) |
|
|
R/W |
Software configuration of PCIE_G0 operating modes 0: working in x8 mode 1: working in x4 mode |
|
|
R/W |
Set the high four bits of PHY to enter the low-power mode |
|
|
R/W |
Set PHY low four bits to enter low-power mode |
4.18. PCIE_G0 PHY LO Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY LO internal control register. This register controls the the lower 4 data links (lane0-3) of PCIE_G0.
Address Offset: 05F0-05F3h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
PHY Configuration Address |
Address Offset: 05F4-05F7h
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
RO |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
Start a read operation or a write operation.
|
4.19. PCIE_G0 PHY HI Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY HI internal control register. This register controls the the high 4 data links (lane4-7) of PCIE_G0.
Address Offset: 05F8-05FBh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY configuration address |
Address Offset: 05FC-05FFh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register |
|
|
R/W |
0 - Read or write to this set of registers will trigger the PHY configuration access operation 1-Writes and writes to this set of registers do not trigger a PHY configuration access operation, only a simple register register read/write |
|
|
R/W |
Start a read operation or a write operation. 0: Read operation 1: Write operation |
4.20. PCIE_G1 PHY Configuration Register
This set of registers contains the control signals for PCIE_G1 PHY.
Address Offset: 0608-060Bh
Attribute: R/W,RO
Default value: 0006_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
Enable software to configure the operating mode of PCIE_G1 0: the operating mode is determined by the hardware pins 1: The operating mode is determined by the software configuration (bit26) |
|
|
R/W |
Software configuration of PCIE_G1 operating modes 0: working in x8 mode 1: working in x4 mode |
|
|
R/W |
Set the high four bits of PHY to enter the low-power mode |
|
|
R/W |
Set PHY low four bits to enter low-power mode |
4.21. PCIE_G1 PHY LO Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY LO internal control register. This register controls the the lower 4 data links (lane0-3) of PCIE_G1.
Address Offset: 0610-0613h
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 0614-0617h
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
PHY One Access Complete indicates that the read or write to the PHY is complete. Write completion indicates that the write Read completion indicates that the read data has been returned to the phy_cfg_data register. |
|
|
R/W |
0 - Read or write to this group of registers will trigger the PHY configuration access operation 1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, only a simple register read or write |
|
|
R/W |
4.22. PCIE_G1 PHY HI Access Configuration Register
This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY HI internal control register. This register controls the high 4 data links (lane4-7) of PCIE_G1.
Address Offset: 0618-061Bh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configures the read and write data. In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 061C-061Fh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register |
|
|
R/W |
|
|
|
R/W |
Start a read operation or a write operation.
|
4.23. SATA0 PHY Configuration Register
This register is used to configure some control parameters of SATA0 PHY.
Address Offset: 0740-0743h
Attribute: R/W
Default value: FF9F_0403h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Link Reset |
|
|
R/W |
PHY Software Reset 0:Unreset 1: Hold reset |
|
|
R/W |
PHY Reference Clock Selection
|
|
|
R/W |
Reserved |
Address Offset: 0744-0747h
Attribute: R/W
Default value: 7FFF_FFFFh
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY Powerdown |
4.24. SATA0 PHY Access Configuration Register
This group of registers is used to control the generation of configuration access operations to the SATA0 PHY internal control registers.
Address Offset: 0748-074Bh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 074C-074Fh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
RO |
|
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register |
|
|
R/W |
0 - Reading or writing to this set of registers triggers a PHY configuration access operation 1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, but rather acts as a read or write operation to this register |
|
|
R/W |
Start a read operation or a write operation.
|
4.25. SATA1 PHY Configuration Register
This register is used to configure some control parameters of SATA1 PHY.
Address Offset: 0750-0753h
Attribute: R/W
Default value: FF9F_0403h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Link Reset |
|
|
R/W |
PHY Software Reset
|
|
|
R/W |
PHY Reference Clock Selection
|
|
|
R/W |
Reserved |
Address Offset: 0754-0757h
Attribute: R/W
Default value: 7FFF_FFFFh
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY Powerdown |
4.26. SATA1 PHY Access Configuration Register
This group of registers is used to control the generation of configuration access operations to the SATA1 PHY internal control registers.
Address Offset: 0758-075Bh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 075C-075Fh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register |
|
|
R/W |
0 - Reading or writing to this set of registers triggers a PHY configuration access operation 1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, but rather acts as a read or write operation to this register |
|
|
R/W |
Start a read operation or a write operation. 0: Read operation 1: Write operation |
4.27. SATA2 PHY Configuration Register
This register is used to configure some control parameters of SATA2 PHY.
Address Offset: 0760-0763h
Attribute: R/W
Default value: FF9F_0403h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Link Reset |
|
|
R/W |
PHY Software Reset 0: Release reset 1: Hold reset |
|
|
R/W |
PHY Reference Clock Selection 0: Use internal reference clock 1: Use external reference clock |
|
|
R/W |
Reserved |
Address Offset: 0764-0767h
Attribute: R/W
Default value: 7FFF_FFFFh
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY Powerdown |
4.28. SATA2 PHY Access Configuration Register
This group of registers is used to control the generation of configuration access operations to the SATA2 PHY internal control registers.
Address Offset: 0768-076Bh
Attribute: R/W
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register. |
|
|
R/W |
PHY Configuration Address |
Address Offset: 076C-076Fh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
PHY Configuration Reset, High Active |
|
|
RO |
PHY Configuration Status Machine Status Indication |
|
|
R/W |
PHY One access completion indicates the completion of this read/write to the PHY. Write completion indicates that the write indicates that the read data has been written to the internal register of PHY, and the read completion indicates that the read data has been returned to the phy_cfg_data register. |
|
|
R/W |
|
|
|
R/W |
Start a read operation or a write operation.
|
4.29. Memory Capacity Configuration Register
This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable. The number of 1’s represents the memory capacity. The default memory capacity is 256MB.
Address Offset: 3838-383Bh
Attribute: R/W
Default value: 0FFF_FFFFh
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
The lower
|
Address Offset: 383C-383Fh
Attribute: R/W,
Default value: 0000_0000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
The high
|
4.30. Bridge Identity register
This register contains the identification ID and revision number of the bridge.
Address Offset: 3FF8-3FFBh
Attribute: RO
Default value: See the description in the table below
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Bridge fixed ID (0x7A). |
|
|
RO |
Bridge Variable ID. |
Address Offset: 3FFC-3FFFh
Attribute: RO
Default value: See the description in the table below
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Bridge piece revision number. |
|
|
RO |
Reserved |
5. Interrupt Controller
The bridge chip has an integrated advanced programmable interrupt controller.
The internal interrupt controller supports up to 64 interrupt sources and two interrupt outputs.
The bridge supports interrupt transmission via both interrupt lines and HT messages.
In the interrupt line method, the bridge’s interrupt output pins are connected to the processor’s interrupt input pins, and the processor is interrupted via the interrupt pins.
In the HT message method, no additional interrupt pin connection is required, and the bridge sends the interrupt vector to the processor’s HT controller register by means of an HT packet, and the processor is interrupted by the HT controller interrupt.
The bridge chip supports the use of only one of these two interrupt methods and is valid for all 64 interrupt sources simultaneously.
The bridge supports outputting dual interrupts, meaning that interrupt information can be routed to both processors. The correspondence between interrupt sources and interrupt outputs is configurable, and this configuration is valid for both interrupt line and HT message packet interrupt modes.
In interrupt line interrupt mode, the interrupt lines of all interrupt-capable devices inside the bridge chip are sent directly to the bridge chip’s interrupt controller, and external PCIE devices send interrupts to the bridge chip’s internal PCIE controller via legacy interrupts. The bridge’s interrupt controller finally interrupts the processor via the bridge’s interrupt pin signal.
In HT message interrupt mode, all devices inside the bridge except the PCIE send interrupt information to the interrupt controller of the bridge via the interrupt line, and the interrupt controller converts the interrupt information into HT message packets and sends them to the processor via the HT bus.
For PCIE devices, there are two interrupt modes, one is that the device still uses legacy interrupt and sends the interrupt information to the interrupt controller of the bridge through the interrupt line of the PCIE controller of the bridge, and the interrupt controller is responsible for converting the interrupt information into HT message packets;
the other is to enable the MSI interrupt function of the PCIE device, and the MSI interrupt message of the device passes through the PCIE controller of the bridge.
The other is to enable the MSI interrupt function of the PCIE device, and the device’s MSI interrupt messages are converted into HT packets by the conversion module inside the bridge’s PCIE controller.
Note that in the latter mode, the interrupt packets of the PCIE device do not support interrupt routing and can only be sent to the HT lo controller of the bridge.
The figure above illustrates the hardware modules and processes involved in interrupts using the 3A+7A computer system as an example.
The figure shows the process of the two interrupt methods, the upper part shows the interrupt through the interrupt line INTn0, and the lower part shows the interrupt through the HT message packet.
The interrupt intX from the device (except for PCIE devices operating in MSI mode) is sent to the 7A internal interrupt controller, where it is routed to the bridge pin or converted into an HT packet and sent to the 3A’s HT controller, which receives the interrupt through the external interrupt pin or HT controller interrupt,
and is routed through the interrupt to The interrupt controller of 3A receives the interrupt through external interrupt pin or HT controller interrupt and interrupts a processor core through interrupt route.
The address space of the bridge interrupt controller is 4KB, and the starting address (internal space of the bridge) is configured by the BIOS.
5.1. Interrupt Source Assignment
The internal devices of the bridge chip are connected to the interrupt controller via interrupt lines. The interrupt pin assignment of the interrupt controller is shown in the follow Table. AC97 controller and HDA controller share one interrupt pin, GPIO0-3 share one interrupt pin, and other GPIOs share one interrupt pin.
| Interrupt Pins | Interrupt Source | Interrupt Pins | Interrupt Source |
|---|---|---|---|
|
- |
|
|
|
- |
|
|
|
- |
|
|
|
- |
|
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- |
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|
- |
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|
- |
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|
- |
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- |
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- |
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- |
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- |
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- |
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- |
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5.2. Description of Interrupt-related Registers
The bridge chip’s interrupt controller has a set of control and status registers for each interrupt source.
| Register Name | Length | Read/Write | Description | Default Value |
|---|---|---|---|---|
|
|
R/W |
Interrupt Mask Register.
|
|
|
|
R/W |
|
|
|
|
R/W |
Trigger mode setting register.
|
|
|
|
WO |
Edge-triggered interrupt clear register. Write |
N/A |
|
|
R/W |
Interrupt distribution mode control register (used in conjunction with {
|
|
|
|
R/W |
Interrupt distribution mode control register (used in conjunction with AUTO_CTRL0). {
|
|
|
|
R/W |
Interrupt Routing Register. Used to configure which processor to route this interrupt to. This register is organized in the form of a bitmap. Bit0: Routed to INTn0/HT controller lo; bit1: Routed to INTn1/HT controller hi. bit7:2: Reserved. |
|
|
|
R/W |
HT message packet interrupt vector register. |
See below |
|
|
RO |
Routing to the interrupt status (in service) register of
|
|
|
|
RO |
Routing to INTn1’s interrupt status (in service) register.
|
|
|
|
RO |
Interrupt request register.
|
|
|
|
RO |
Interrupt status (in service) register.
|
|
|
|
R/W |
Interrupt level trigger polarity selection register. For the level trigger type.
|
|
The address distribution of the registers related to the interrupt controller is shown in the following table
Interrupt register address distribution
| Register Name | Address Offset | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Interrupt controller identification register |
|
|
R/W |
Interrupt Mask Register |
|
|
R/W |
HT message packet interrupt enable register |
|
|
R/W |
Trigger mode setting register |
|
|
WO |
Edge-triggered interrupt clear register |
|
|
R/W |
Interrupt distribution mode control register 0 |
|
|
R/W |
Interrupt distribution mode control register 1 |
|
|
R/W |
Interrupt routing register [ 7- 0] |
|
|
R/W |
Interrupt routing register [15- 8] |
|
|
R/W |
Interrupt Routing Register [23-16] |
|
|
R/W |
Interrupt Routing Register [31-24] |
|
|
R/W |
Interrupt routing register [39-32] |
|
|
R/W |
Interrupt Routing Register [47-40] |
|
|
R/W |
Interrupt Routing Register [55-48] |
|
|
R/W |
Interrupt Routing Register [63-56] |
|
|
R/W |
HT Interrupt Vector Register [ 7- 0] |
|
|
R/W |
HT Interrupt Vector Register [15- 8] |
|
|
R/W |
HT Interrupt Vector Register [23-16] |
|
|
R/W |
HT Interrupt Vector Register [31-24] |
|
|
R/W |
HT Interrupt Vector Register [39-32] |
|
|
R/W |
HT Interrupt Vector Register [47-40] |
|
|
R/W |
HT Interrupt Vector Register [55-48] |
|
|
R/W |
HT Interrupt Vector Register [63-56] |
|
|
RO |
Interrupt status (in service) register routed to |
|
|
RO |
Interrupt status (in service) register routed to |
|
|
RO |
Interrupt request register |
|
|
RO |
Interrupt Status (In Service) Register |
|
|
R/W |
Interrupt trigger level selection register |
Interrupt controller identification register
Address Offset: 000-003h
Attribute: RO
Default value: 07000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Interrupt Controller ID |
|
|
RO |
Reserved |
Address Offset: 004-007h
Attribute: RO
Default value: 003F0001h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
RO |
The number of interrupt sources supported. The actual number of interrupts is equal to the value of this field plus |
|
|
RO |
Reserved |
|
|
RO |
Interrupt controller version number |
Interrupt mask register
Address Offset: 020-023h
Attribute: R/W
Default value: FFFFFFFFh
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low 32 bits of the interrupt mask register (bit[31:0]) |
Address Offset: 024-027h
Default value: FFFFFFFFh
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High 32 bits of the interrupt mask register (bit[63:32]) |
HT interrupt message packet enable register
Address Offset: 040-043h
Default value: 00000000h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low 32 bits (bit[31:0]) of the HT Interrupt Message Packet Enable Register |
Address Offset: 044-047h
Default value: 00000000h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High 32 bits (bit[63:32]) of the HT Interrupt Message Packet Enable Register |
Interrupt trigger control register
Address Offset: 060-063h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low 32 bits of the interrupt trigger control register (bit[31:0]) |
Address Offset: 064-067h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High 32 bits of the interrupt trigger control register (bit[63:32]) |
Interrupt clear register
Address Offset: 080-083h
Attribute: WO
Default value: N/A
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
Low 32 bits of the interrupt clear register (bit`[31:0]`) |
Address Offset: 084-087h
Attribute: WO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
High 32 bits of the interrupt clear register (bit`[63:32]`) |
INT_AUTO_CTRL0 register
Address Offset: 0C0-0C3h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low 32 bits (bit`[31:0] |
Address Offset: 0C4-0C7h
Default value: 00000000h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High |
INT_AUTO_CTRL1 register
Address Offset: 0E0-0E3h
Default value: 00000000h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low |
Address Offset: 0E4-0E7h
Default value: 00000000h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High |
Interrupt routing configuration register
Address Offset: 100-103h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 104-107h
Default value: 01010101h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 108-10Bh
Default value: 01010101h
Attribute: R/W
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 10C-10Fh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 110-113h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 114-117h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 118-11Bh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PWM3 Interrupt Routing Configuration Register |
|
|
R/W |
PWM2 Interrupt Routing Configuration Register |
|
|
R/W |
PWM1 Interrupt Routing Configuration Register |
|
|
R/W |
PWM0 Interrupt Routing Configuration Register |
Address Offset: 11C-11Fh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Thsensor Interrupt Routing Configuration Register |
|
|
R/W |
GPU Interrupt Routing Configuration Register |
|
|
R/W |
GMEM Interrupt Routing Configuration Register |
|
|
R/W |
DC Interrupt Routing Configuration Register |
Address Offset: 120-123h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PCIE_F0 Controller 3 Interrupt Routing Configuration Register |
|
|
R/W |
PCIE_F0 Controller 2 Interrupt Routing Configuration Register |
|
|
R/W |
PCIE_F0 Controller 1 Interrupt Routing Configuration Register |
|
|
R/W |
PCIE_F0 Controller 0 Interrupt Routing Configuration Register |
Address Offset: 124-127h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PCIE_H Controller |
|
|
R/W |
PCIE_H Controller |
|
|
R/W |
PCIE_F1 Controller |
|
|
R/W |
PCIE_F1 Controller |
Address Offset: 128-12Bh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 12C-12Fh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 130-133h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 134-137h
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 138-13Bh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Address Offset: 13C-13Fh
Attribute: R/W
Default value: 01010101h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
HT message packet interrupt vector configuration register
Address Offset: 200-203h
Attribute: R/W
Default value: 03020100h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 204-207h
Attribute: R/W
Default value: 070605040h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 208-20Bh
Attribute: R/W
Default value: 0B0A0908h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
|
|
R/W |
I2C HT Interrupt Vector Configuration Register |
|
|
R/W |
UART HT interrupt vector configuration register |
Address Offset: 20C-20Fh
Attribute: R/W
Default value: 0E0F0D0Ch
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
GMAC1_PMT HT Interrupt Vector Configuration Register |
|
|
R/W |
GMAC1_SBD HT Interrupt Vector Configuration Register |
|
|
R/W |
GMAC0_PMT HT Interrupt Vector Configuration Register |
|
|
R/W |
GMAC0_SBD HT Interrupt Vector Configuration Register |
Address Offset: 210-213h
Attribute: R/W
Default value: 13121110h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
LPC HT Interrupt Vector Configuration Register |
|
|
R/W |
SATA2 HT Interrupt Vector Configuration Register |
|
|
R/W |
SATA1 HT Interrupt Vector Configuration Register |
|
|
R/W |
SATA0 HT Interrupt Vector Configuration Register |
Address Offset: 214-217h
Attribute: R/W
Default value: 17161514h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved |
Address Offset: 218-21Bh
Attribute: R/W
Default value: 1B1A1918h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PWM3 HT Interrupt Vector Configuration Register |
|
|
R/W |
PWM2 HT Interrupt Vector Configuration Register |
|
|
R/W |
PWM1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PWM0 HT Interrupt Vector Configuration Register |
Address Offset: 21C-21Fh
Attribute: R/W
Default value: 1E1F1D1Ch
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Thsensor HT Interrupt Vector Configuration Register |
|
|
R/W |
GPU HT Interrupt Vector Configuration Register |
|
|
R/W |
GMEM HT Interrupt Vector Configuration Register |
|
|
R/W |
DC HT Interrupt Vector Configuration Register |
Address Offset: 220-223h
Attribute: R/W
Default value: 43424140h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PCIE_F0 Controller 3 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_F0 Controller 2 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_F0 Controller 1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_F0 Controller 0 HT Interrupt Vector Configuration Register |
Address Offset: 224-227h
Attribute: R/W
Default value: 47464544h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PCIE_H Controller 1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_H Controller 0 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_F1 Controller 1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_F1 Controller 0 HT Interrupt Vector Configuration Register |
Address Offset: 228-22Bh
Attribute: R/W
Default value: 4B4A4948h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
PCIE_G1 Controller 1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_G1 Controller 0 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_G0 Controller 1 HT Interrupt Vector Configuration Register |
|
|
R/W |
PCIE_G0 Controller 0 HT Interrupt Vector Configuration Register |
Address Offset: 22C-22Fh
Attribute: R/W
Default value: 4F4E4D4Ch
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
ACPI HT Interrupt Vector Configuration Register |
|
|
R/W |
TOY2 HT Interrupt Vector Configuration Register |
|
|
R/W |
TOY1 HT Interrupt Vector Configuration Register |
|
|
R/W |
TOY0 HT Interrupt vector configuration register |
Address Offset: 230-233h
Attribute: R/W
Default value: 53525150h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
USB1 OHCI Controller HT Interrupt Vector Configuration Register |
|
|
R/W |
USB1 EHCI Controller HT Interrupt Vector Configuration Register |
|
|
R/W |
USB0 OHCI Controller HT Interrupt Vector Configuration Register |
|
|
R/W |
USB0 EHCI Controller HT Interrupt Vector Configuration Register |
Address Offset: 234-237h
Attribute: R/W
Default value: 57565554h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
HPET HT Interrupt Vector Configuration Register |
|
|
R/W |
RTC2 HT Interrupt Vector Configuration Register |
|
|
R/W |
RTC1 HT Interrupt Vector Configuration Register |
|
|
R/W |
RTC0 HT Interrupt Vector Configuration Register |
Address Offset: 238-23Bh
Attribute: R/W
Default value: 5B5A5958h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
GPIO high bit (bit[56:4]) HT interrupt vector configuration register |
|
|
R/W |
AC97/HDA Controller HT Interrupt Vector Configuration Register |
|
|
R/W |
AC97 DMA1 HT Interrupt vector configuration register |
|
|
R/W |
AC97 DMA0 HT Interrupt vector configuration register |
Address Offset: 23C-23Fh
Attribute: R/W
Default value: 5F5E5D5Ch
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
|
|
R/W |
|
Interrupts routed to INTn0 are in the Service Status Register
Address Offset: 300-303h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Interrupts routed to INTn0 are in the lower |
Address Offset: 304-307h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
The interrupt routed to INTn0 is in the high 32 bits of the service status register (bit`[63:32]`) |
Interrupts routed to INTn1 are in the service status segiste
Address Offset: 320-323h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Interrupts routed to INTn1 are in the lower 32 bits of the service status register (bit`[31:0]`) |
Address Offset: 324-327h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
The interrupt routed to INTn1 is in the high |
Interrupt request register
Address Offset: 380-383h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low |
Address Offset: 384-387h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High 32 bits of the interrupt request register (bit`[63:32]`) |
Interrupt in service status register
Address Offset: 3A0-3A3h
Attribute: RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Interrupt in the lower |
Address Offset: 3A4-3A7h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Interrupt in the high 32 bits of the service status register (bit`[63:32]`) |
Interrupt level trigger polarity register
Address Offset: 3E0-3E3h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Low |
Address Offset: 3E4-3E7h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
High |
5.3. Device Interrupt Types
For the bridge chip, AC97 DMA interrupts are edge triggered, gpio interrupts can be configured to be level triggered or edge triggered as needed, and the rest of the interrupts are level triggered and active high.
For PCIE devices, one way is to use the interrupt line of the PCIE controller inside the bridge to transmit the interrupt; the other way is to use the MSI interrupt of the PCIE device directly.
In the PCIE MSI interrupt method, when the PCIE controller inside the bridge receives an MSI interrupt, it converts it directly into an HT interrupt message packet to send to the HT controller. Therefore, the software needs to be careful to distinguish the MSI interrupt vector of the PCIE device from the HT interrupt vector configured by the internal device of the bridge.
5.4. Interrupt Distribution Modes
The bridge supports dual interrupt outputs, so that different interrupt sources or multiple interrupts from the same interrupt source can be distributed between the two interrupt outputs. The bridge chip supports interrupt hardware load balancing, which allows interrupts to be distributed between the two outputs preset by software in four modes.:
-
Fixed distribution mode - Distribution is done according to the routing method configured in the interrupt routing configuration register. In this mode, the routing configuration register must be one-hot encoded, meaning that an interrupt can only be routed to one interrupt output.
-
Rotating distribution mode - In this mode, each new interrupt generated is routed to the next valid interrupt output according to the route vector configuration in the Route_Entry register. The route to the next valid interrupt output is configured in the Route_Entry register.
-
Idle distribution mode - jumps to an idle interrupt output. In this mode, when each new interrupt is generated, it first detects if there is already an unprocessed interrupt on the next interrupt output according to the routing vector configuration in the Entry register, and if not, it is routed to that interrupt output; if there is already an unprocessed interrupt on the next interrupt output, it continues to detect the next processor core.
-
Busy distribution mode - the current interrupt output is busy then jumps to its left (0→1→2→3) candidate interrupt output. When each new interrupt is generated in this mode, it first detects whether there is already an unprocessed interrupt on the interrupt output of the last interrupt, and if not, continues to interrupt that interrupt output, and if there is an unprocessed interrupt, it is routed to the next interrupt output as configured in the Entry register. It should be noted that once AUTO_CTRL0/1 has been configured, it should not be modified in the middle of the run. It is recommended that the software use fixed distribution mode.
5.5. Detailed Description of Interrupt Handling Process
In the interrupt line interrupt mode, the interrupt controller of the bridge chip receives the device interrupt and sets the corresponding interrupt output pin low according to the interrupt routing configuration. The processor receives the interrupt through the interrupt input pin, and the processor obtains the current interrupt source routed to itself by reading the corresponding ISR (interrupt in service register) register within the bridge chip interrupt controller. The interrupt processing process is:
-
The interrupt controller of the bridge receives the device interrupt; (hardware)
-
The interrupt controller of the bridge chip sets the interrupt output pin low; (hardware)
-
The processor’s interrupt controller receives the interrupt pin interrupt; (hardware)
-
The processor turns off the interrupt. (software)
-
The processor reads its own interrupt controller and learns that it is an external interrupt; (software)
-
The processor reads the interrupt controller of the bridge chip to get the interrupt vector; (software)
-
The processor writes the interrupt controller of the bridge chip to mask the corresponding interrupt source; (software)
-
The processor opens the interrupt. (software)
-
The processor calls the interrupt service program to handle the interrupt; (software)
-
The processor writes the bridge chip’s interrupt controller to clear edge-triggered interrupts; (software)
-
The processor writes the bridge chip’s interrupt controller to turn on the corresponding interrupt source. (Software)
-
The processor interrupt returns. (Software)
In the HT message packet interrupt method, the interrupt controller and PCIE controller of the bridge receive the device interrupt and can send the interrupt vector directly to the HT controller of the processor, thus avoiding the process of the processor querying the internal interrupt vector of the bridge. The interrupt processing process is as follows.
-
The interrupt controller of the bridge receives the device interrupt; (hardware)
-
The interrupt controller of the bridge slices sends the interrupt vector to the HT controller of the processor; (hardware)
-
The processor’s interrupt controller receives the HT interrupt; (hardware)
-
The processor turns off the interrupt. (software) 5.
-
The processor reads its own interrupt controller and learns that it is an HT interrupt; (software)
-
The processor reads its own HT controller to get the interrupt vector; (software)
-
The processor writes its own HT controller to clear the interrupt; (software)
-
The processor opens the interrupt. (software) 9.
-
The processor calls the interrupt service program to handle the interrupt; (software)
-
The processor writes the bridge chip’s interrupt controller to clear the interrupt (not required if it is an MSI interrupt issued by a PCIE device). (software)
-
The processor interrupt returns. (Software)
The software can configure the HT interrupt vector corresponding to the internal devices of the bridge chip.
6. HPET Controller
The HPET controller is compatible with standard specifications. Internally, it includes a 64-bit main counter and three 32-bit timers (comparators). Of the three timers, timer 0 supports both periodic-capable and non-periodic interrupts, while timers 1 and 2 support only non-periodic interrupts.
6.1. Access Address
The address space size of the HPET controller is 4KB, and the starting address (internal space of the bridge chip) is configured by the BIOS. The physical address composition of the internal registers of the HPET controller is as follows:
| Address bits | Composition | Remarks |
|---|---|---|
|
|
Reserved |
|
|
Internal register address |
Note: The HPET controller only supports 4-byte accesses. Software that needs to use the HPET’s 64-bit master counter as a timestamp needs to be careful to handle the data rounding introduced by reading the high and low 32-bit values in two separate readings.
6.2. Description of Registers
| Register Offset Address | Description |
|---|---|
|
General Capabilities and ID Register |
|
Reserved |
|
General Configuration Register |
|
Reserved |
|
General Interrupt Status Register |
|
Reserved |
|
Main Counter Value Register |
|
Timer |
|
Timer |
|
Reserved |
|
Timer |
|
Timer |
|
Reserved |
|
Timer |
|
Timer |
|
Reserved |
General Capabilities and ID Register
Address Offset: 00-07h
Attribute: RO
Default value: See description
Size:`8`
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Timing frequency of the master timer in fps ( |
RO |
|
|
Manufacturer ID. value: |
RO |
|
|
Reserved |
RO |
|
|
The width of the master timer. This chip is a
|
RO |
|
|
Number of timers; the value of this field indicates the number of the last timer. This chip contains This chip contains |
RO |
|
|
Version number; value: |
RO |
General Configuaration Register
Address Offset: 10-17h
Attribute: RO, R/W
Default value: 0h
Size:8
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Reserved |
RO |
|
|
HPET enable control.
|
General Interrupt Status Register
Address Offset: 20-27h
Attribute: RO, R/WC
Default value: 0h
Size:8
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Reserved |
RO |
|
|
Timer |
R/WC |
|
|
Timer |
R/WC |
|
|
Timer When the timer’s interrupt trigger mode is level-triggered, this timer defaults to |
R/WC |
The interrupt trigger mode of each timer is determined by the Tn_TYPE_CNF bit of the respective Configuartion and Capability register.
Main Counter Value Register
Address Offset: F0-F7h
Attribute: R/W
Default value: 0h
Size:`8`
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Master timer. Modifying the value of this register is only allowed when the main timer stops timing. |
R/W |
Timer 0 Configuration and Capabilities Registe
Address Offset: 100-107h
Attribute: RO, R/W
Default value: 10h
Size:`8`
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Reserved |
RO |
|
|
Timer |
RO |
|
|
Reserved |
RO |
|
|
Timer |
R/W |
|
|
Timer 0 Width indication.
|
RO |
|
|
Timer
|
RO |
|
|
Timer 0 cycle interrupt configuration.
If the corresponding
|
R/W |
|
|
Enable Timer |
R/W |
|
|
Timer
|
R/W |
|
|
Reserved |
RO |
Timer 0 Comparator Value Register
Address Offset: 108-10Fh
Attribute: R/W
Default value: FFFFFFFFh
Size:`8`
| Bit Field | Name | Description | Read/Write |
|---|---|---|---|
|
|
Reserved |
RO |
|
|
The value of the timer |
R/W |
Timer 1 Configuration and Capabilities Registe
Address Offset: 120-127h
Attribute: RO, R/W
Default value: 00h
Size:`8` Timer 1 configuration and function registers. Same as Timer 0.
Timer 1 Comparator Value Register
Address Offset: 128-12Fh
Attribute: R/W
Default value: FFFFFFFFh
Size:`8` Timer 1 comparator value. Same as Timer 0.
Timer 2 Configuration and Capabilities Registe
Address Offset: 140-147h
Attribute: RO, R/W
Default value: 00h
Size: 8
Timer 2 configuration and function registers. Same as Timer 0.
Timer 2 Comparator Value Register
Address Offset: 148-14Fh
Attribute: R/W
Default value: FFFFFFFFh
Size:`8`
Timer 2 comparator value. Same as Timer 0.
7. HT Controller
The bridge HT interface supports a maximum bi-directional 16-bit data width and an operating frequency of 2.0 GHz. After the connection is established by automatic system initialization, the user can change the width and operating frequency and re-initialize by modifying the corresponding configuration registers in the protocol.
The main features of the bridge HT interface are as follows:
-
Support HT1.0/3.0 protocol
-
Support 200/400/800/1600/2000 MHz operating frequency
-
Support 8/16 bit width
-
Support dual processors with bridge chip direct connection (each link can only work in 8-bit mode)
7.1. HT User Guide
7.1.1. HT Working Mode
When chip pin HT_8x2 is configured to 0, the bridge operates in single mode, where only one processor is directly connected to the bridge via the HT bus, and only one HT controller (HT lo) is operating inside the bridge, while the other HT controller (HT hi) is not available.
The HT link can operate in either 8-bit or 16-bit mode, and the software can configure the data width used (the maximum available width also depends on the PCB hardware connection), when the data link is controlled by controller lo. The data link is controlled by the controller lo.
When the chip pin HT_8x2 is configured to 1, the bridge operates in dual mode, where two processors can be connected directly to the bridge via the HT bus, and the two HT controllers inside the bridge are operating simultaneously, controlling the low 8 bits and high 8 bits of the data link respectively. Software can control both HT controllers via the HT bus of both processors. When operating in dual mode, the software needs to configure the HT DMA routing configuration (see section 4.1 HT Clock Enable and DMA Routing Configuration) to send DMA accesses to the corresponding HT controller.
7.1.2. HT Address Space
The address space for processor accesses is described in Section 3.
The HT module has several internal address windows for configuring CPU accesses and DMA accesses. For CPU accesses, the bridge chip acts as the accessee and the corresponding configuration window is called the receive window; for DMA accesses, the bridge chip acts as the access initiator and the corresponding window is called the send window.
The receive window consists of two types: the P2P access window and the normal access window. Accesses that fall within the P2P access window are forwarded directly back to the HT bus as P2P commands and are not sent to the internal devices of the bridge chip; accesses that fall within the normal access window are sent to the internal devices of the bridge chip as accesses to the internal devices of the bridge chip. The P2P access window has a higher priority than the normal access window. Accesses that do not hit in either of the two types of receive windows are forwarded directly back to the HT bus as P2P commands.
DMA accesses are sent out through the HT’s non-Post channel by default, and the Post send window is set internally in the bridge to send DMA accesses out through the HT’s Post channel. That is, DMA accesses that hit in the Post send window are sent to the HT bus via the HT’s Post channel, and DMA accesses that do not hit in the Post send window are sent to the HT bus via the HT’s non-Post channel. In general, the Post send window should not be enabled and all DMA accesses should be sent out through the HT’s non-Post channel.
7.2. HT Configuration Register
HT Configuration Register
| Address Offset | Abbreviations | Description | Default value | Read/Write |
|---|---|---|---|---|
|
|
Vendor ID |
|
RO |
|
|
Device ID |
|
RO |
|
|
PCI Command |
|
R/W, RO |
|
|
PCI Status |
|
RO |
|
|
Revision ID |
|
RO |
|
|
Programming Interface |
|
RO |
|
|
Sub Class Code |
|
RO |
|
|
Base Class Code |
|
RO |
|
|
Cache Line Size |
|
RO |
|
|
Header Type |
|
RO |
|
|
Subsystem Vendor ID |
|
RO |
|
|
Subsystem Identification |
|
RO |
|
|
Capabilities Pointer |
|
RO |
|
|
Interrupt Line |
|
R/W |
|
|
Interrupt Pin |
|
RO |
|
|
Bridge Control Register |
|
R/W |
|
|
Device ID Command Register |
|
R/W, RO |
|
|
Link Status and Control Register 0 |
|
R/W |
|
|
Link Width Status and Control Register 0 |
|
R/W |
|
|
HT Revision ID |
|
RO |
|
|
Link Frequency Status and Control Register 0 |
|
R/W, RO |
|
|
Receive Window 0 |
|
R/W |
|
|
Receive Window 1 |
|
R/W |
|
|
Receive Window 2 |
|
R/W |
|
|
Receive Window 3 |
|
R/W |
|
|
Receive Window 4 |
|
R/W |
|
|
Transmit Post Window 0 |
|
R/W,RO |
|
|
Transmit Post Window 1 |
|
R/W,RO |
|
|
Receive P2P Window 0 |
|
R/W,RO |
|
|
Receive P2P Window 1 |
|
R/W,RO |
|
|
HT Pll Control Register |
|
R/W,RO |
Note: Address spaces not listed in the table indicate reservations.
BCTRL-HT bridge control register
Address Offset: 3E-3Fh
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
R/W |
This bit controls the HT reset. 0: unreset. 1: Reset. |
|
|
RO |
Reserved |
DIDCMD - device ID command register
Address Offset: 42-43h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Command Format |
|
|
RO |
Reserved |
|
|
R/W |
Provided to the software for recording the current number of units |
|
|
R/W |
Record the number of IDs used |
LKSC0-Link status control register 0
Address Offset: 44-45h
Attribute: R/W, RO
Default value: 2000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
R/W |
Whether to turn off the HT PHY when the HT bus enters the HT Disconnect state.
|
|
|
RO |
Reserved |
|
|
R/W |
CRC error occurs in high 8 bits |
|
|
R/W |
CRC error occurs on low 8 bits |
|
|
R/W |
HT PHY off control. When in
|
|
|
RO |
HT Bus End |
|
|
RO |
HT bus initialization complete |
|
|
RO |
Connection failure indication |
|
|
RO |
Reserved |
|
|
R/W |
Whether to flood the |
|
|
R/W |
When running an
|
LKWDSC0-Link data width status and control register
Address Offset: 46-47h
Attribute: R/W, RO
Default value: 0011h or 0000h
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
R/W |
Link Sender Width. The value after a cold reset is the maximum width of the current connection, and the value written to this register will take effect after the next hot reset or HT Disconnect.
|
|
|
RO |
Reserved |
|
|
R/W |
Link Sender Width. The value after a cold reset is the maximum width of the current connection, and the value written to this register will take effect after the next hot reset or HT Disconnect.
|
|
|
RO |
The transmitter supports double-word flow control.
|
|
|
RO |
Maximum width of the link transmitter.
|
|
|
RO |
The receiver side supports double-word flow control.
|
|
|
RO |
Maximum width at the receiver end of the link.
Note: When |
LKFREQCFG0-Link frequency configuration register
Address Offset: 4C-4Dh
Attribute: R/W, RO
Default value: 0060h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
RO |
HT bus packet overflow |
|
|
RO |
Protocol error, referring to an unrecognized command received on the HT bus |
|
|
R/W |
HT Bus Operating Frequency Configuration, the configuration value corresponds to the bit of Link Frequency Capability. For example, setting this register to |
|
|
RO |
PLL (0x1F4), this bit has no meaning) |
Address Offset: 4E-4Fh
Attribute: RO
Default value: 0000h
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
The supported HT bus frequency, which produces a different value depending on the external PLL setting (when using the software configuration PLL (0x1F4) is used, this bit is meaningless). Each bit represents an HT bus frequency, and when the bit is 1 it indicates that the frequency is supported; when the bit is 0 it indicates that the frequency is not supported. The frequencies represented by each bit are as follows: bit0:200MHz bit1:300MHz bit2:400MHz bit3:500MHz bit4:600MHz bit5:800MHz bit6:1.0GHz bit7:1.2GHz bit8:1.4GHz bit9:1.6GHz bit10:1.8GHz bit11:2.0GHz bit12:2.2GHz bit13:2.4GHz bit14:2.6GHz bit15:3.2GHz |
RXWIN - receive address window
Receive address window hits are sent to the internal devices of the bridge chip only when the access is hit. The receive address window includes the following fields:
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Window Base Address |
|
|
R/W |
Window Mask |
|
|
R/W |
Window Enable |
|
|
R/W |
Window address conversion enable |
|
|
R/W |
Window converted address high bit of address bit`[53:24]`
When the window is enabled, the address window hit condition is: ( |
RXWIN0-Receive window register 0
Address Offset: 140-147h
Attribute: R/W
Default value: 0000F00080000000h
Size:`64` bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
RXWIN1-Receive window register 1
Address Offset: 148-14Fh
Attribute: R/W
Default value: FDFCFFFF80000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
RXWIN2-Receive window register 2
Address Offset: 150-147h
|Attribute: R/W
Default value: 0000000000000000h
|Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
RXWIN3-Receive window register 3
Address Offset: 158-14Fh
Attribute: R/W
Default value: 0000000000000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
|
|
R/W |
Receive Window |
RXWIN4-Receive window register 4
Address Offset: 160-147h
Attribute: R/W
Default value: 0000000000000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Receive Window |
|
|
|
Receive Window |
|
|
|
Receive Window |
|
|
|
Receive Window |
|
|
|
Receive Window |
TXPOSTWIN - quick send window
Visits hit by the Quick Send window give a direct response, thus speeding up the request for the request initiator. The Quick Send window includes the following fields:
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Window Base Address |
|
|
|
Window Mask |
|
|
|
Window Enable |
|
|
|
Reserved |
When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit`[39:24], the address sent to the HT bus is only 40 bits).
For example, `1111111100000000b,1100000000000000b are all legal configurations, while The number of zeros in MASK indicates the size of the address window.
TXPOSTWIN0-Quick send window register 0
Address Offset: 170-177h
Attribute: R/W,RO
Default value: 0000000000000000h
Size:`64` bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Quick Send Window |
|
|
|
Fast Send Window |
|
|
|
Fast Send Window |
|
|
|
Reserved |
TXPOSTWIN1 - Quick send window register 1
Address Offset: 178-17Fh
Attribute: R/W,RO
Default value: 000000000000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Quick Send Window |
|
|
|
Fast Send Window |
|
|
|
Fast Send Window |
|
|
|
Reserved |
RXP2PWIN-P2P receive window
Accesses hit by the P2P receive window are sent directly back to the HT bus as P2P commands. the P2P receive window has a higher priority than the normal receive window. the P2P receive window includes the following fields.
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Window Base Address |
|
|
|
Window Mask |
|
|
|
Window Enable |
|
|
|
Reserved |
When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit[39:24], the address sent to the HT bus is only 40 bits).
For example, 1111111100000000b,1100000000000000b are legal configurations, while 1011111100000000b,11010000000000b are not. The number of zeros in MASK indicates the size of the address window.
RXP2PWIN0-P2P receive window 0
Address Offset: 180-187h
Attribute: R/W,RO
Default value: 00000`00000000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
P2P Receive Window |
|
|
|
P2P receive window |
|
|
|
P2P receive window |
|
|
|
Reserved |
RXP2PWIN0-P2P receive window 1
Address Offset: 188-18Fh
Attribute: R/W,RO
Default value: 000000000000000h
Size: 64 bit
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
P2P Receive Window |
|
|
|
P2P receive window |
|
|
|
P2P receive window |
|
|
|
Reserved |
Htpllctrl-ht pll control register
This register is used to enable the software configuration of the HT’s PLL, which is used to modify the frequency of the HT PHY and controller.
Address Offset: 1F4-1F7h
Attribute: R/W,RO
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
|
Reserved |
|
|
|
PHY low output crossover |
|
|
|
PHY high output crossover |
|
|
|
HT PLL input frequency division |
|
|
|
HT PLL Multiplier |
|
|
|
Controller output divider |
|
|
|
Reserved |
|
|
|
PLL lock |
|
|
|
Controller clock bypass mode |
|
|
|
PLL Configuration Enable |
|
|
|
0: Disable PLL configuration |
8. MISC Low-speed Devices
MISC low speed devices include: UART, I2C, PWM, ACPI, RTC, and GPIO. these devices run at a fixed frequency of 50MHz.
8.1. MISC Low-speed Devices Configuration Register
The address space size of the MISC low-speed device block is 512KB, and the starting address (internal space of the bridge chip) is configured by the BIOS.
8.2. Internal Device Address Routing
Multiple devices within the MISC low-speed device block are distinguished by the bits [18:16] of the address bits, and different devices support only specific types of access. The device routing and supported access types are shown in the following table.
| bit[18:16] | 0 | 1 | 2 | 5 | 6 |
|---|---|---|---|---|---|
Device |
|
|
|
|
|
Read/Write |
|
|
|
|
|
For UART, I2C, PWM, and ACPI/RTC, they require further routing due to the inclusion of multiple controllers. The internal routing of these device blocks is shown in the fllow table The number of routing address bits required varies from one device block to another.
| 0 | 1 | 2 | 3 | 4 | 5 | |
|---|---|---|---|---|---|---|
|
|
|
|
|
- |
- |
|
|
|
|
|
|
|
|
|
|
|
|
- |
- |
|
|
|
- |
- |
- |
- |
These low-speed devices are described separately in subsequent sections.
9. UART Controller
The integrated UART controller of the bridge chip complies with the RS232 standard and the controller is designed to be compatible with the 16550A. The internal clock frequency of the UART controller is 50 MHz and the maximum baud rate supported by the UART bus is 460800.
The bridge chip integrates four UART controllers, which are arranged in the UART module. In addition, UART1, UART2 and UART3 can only work in two-wire UART mode, and UART0 can work in full-function UART mode or two-wire UART mode. In addition, UART can be multiplexed as GPIO function and some UART pins can be multiplexed as I2C function. The pin multiplexing configuration registers related to UART are described in Section 4.4.
|
|
|
|
|
|||
|
|
|
|
9.1. Access Address
The access base address of the UART controller is the base address of the MISC low-speed device block plus offset 0x0. Note: The UART module supports byte access only.
The 4 UART controllers are distinguished by bit [9:8], and the internal physical address division of the UART module is shown in the following table.
| Address bit | Composition | Remarks |
|---|---|---|
|
|
|
|
|
|
|
|
|
9.2. Description of Registers
Data register (DAT)
Offset: 0x00
Reset value: 0x00
| Bit Field | Name | Length | Read/Write |
|---|---|---|---|
|
|
Tx FIFO |
|
Interrupt enable register (IER)
Offset: 0x01
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Reserved |
|
|
|
R/W |
Modem Status Interrupt Enable
|
|
|
|
R/W |
Receiver line status interrupt enable
|
|
|
|
R/W |
Transmission save register is air break enable
|
|
|
|
R/W |
Receive valid data interrupt enable
|
Interrupt identification register (IIR)
Offset: 0x02
Reset value: 0xc1
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R |
Reserved |
|
|
|
R |
Interrupt source indication bits, see the following table for details |
|
|
|
R |
Interrupt bits |
Interrupt control menu
| Bit 3 | Bit 2 | Bit 1 | Priority | Interrupt Type | Interrupt Source | Interrupt Reset Control |
|---|---|---|---|---|---|---|
|
|
|
|
Receive line status |
parity, overflow or frame errors. |
Read LSR |
|
|
|
|
Valid data received |
or interrupt interrupt |
The number of characters in the FIFO is lower than the value of the trigger |
|
|
|
|
Receive timeout |
The number of characters in the FIFO reaches the level of a trigger |
Read the receive FIFO |
|
|
|
|
Transmission save register is empty |
There is at least one character in the FIFO, but no operation, including read and write operations, within 4 characters |
Write data to THR or multi-IIR |
|
|
|
|
Modem Status |
Transfer save register is empty |
Read MSR |
FIFO control register (FCR)
Offset: 0x02
Reset value: 0xc0
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
W |
Receive trigger value for interrupt request from FIFO
|
|
|
|
W |
Reserved |
|
|
|
W |
Clears the contents of the transmit FIFO and resets its logic |
|
|
|
W |
Clears the contents of the receive FIFO and resets its logic |
|
|
|
W |
Reserved |
Line control register (LCR)
Offset: 0x03
Reset value: 0x03
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Crossover latch access bits
|
|
|
|
R/W |
Interrupt control bit
|
|
|
|
R/W |
Specify the parity bit
|
|
|
|
R/W |
Parity Bit Selection
|
|
|
|
R/W |
Parity bit enable
|
|
|
|
R/W |
Define the number of bits to generate stop bits
|
|
|
|
R/W |
Set the number of bits per character
|
MODEM control register (MCR)
Offset:`0x04`
Reset value:`0x00`
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
W |
Reserved |
|
|
|
W |
Loopback mode control bits
In loopback mode, the TXD output is always 1 and the output shift register is connected directly to the input shift register. Other connections are as follows: DTR - DSR RTS - CTS Out1 - RI Out2 - DCD |
|
|
|
W |
Connects to the DCD input in loopback mode |
|
|
|
W |
Connects to the RI input in loopback mode |
|
|
|
W |
RTS signal control bit |
|
|
|
W |
DTR signal control bit |
Line status register (LSR)
Offset:`0x05`
Reset value:`0x00`
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R |
Error indication bit
|
|
|
|
R |
Transfer to empty indicates bit
|
|
|
|
R |
Transfer FIFO bit null indicates bit
|
|
|
|
R |
Interrupt interrupt indication bit
|
|
|
|
R |
Frame error indication bits
|
|
|
|
R |
Parity bit error indication bit
|
|
|
|
R |
Data overflow indication bit
|
|
|
|
R |
Receive data valid indication bit
|
When reading this register, LSR[4:1] and LSR[7] are cleared to zero, LSR[6:5] is cleared when writing data to the transmit FIFO, and LSR[0] is judged for the receive FIFO.
MODEM status register (MSR)
Offset: 0x06
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R |
The inverse of the DCD input value, or to Out2 in loopback mode |
|
|
|
R |
The inverse of the RI input value, or to OUT1 in loopback mode |
|
|
|
R |
The inverse of the DSR input value, or to DTR in loopback mode |
|
|
|
R |
The inverse of the |
|
|
|
R |
DDCD indication bit |
|
|
|
R |
RI edge detection, |
|
|
|
R |
DDSR indication bit |
|
|
|
R |
DCTS indication bit |
Frequency divider latch
Offset: 0x00
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Store the lower |
Offset:0x01
Reset value:0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Store the high |
The value of the crossover latch {MSB,LSB} is calculated as 50MHz/16/baud rate. For example, if you want to configure a serial port baud rate of 115200, the value of the divider latch = 50,000,000/16/115,200 ≈ 27.
10. I2C Controller
A total of 6 I2C controllers are integrated into the bridge, and the I2C controllers operate at 50MHz.
The maximum transfer rate supported by the I2C bus is 400kbps.
10.1. Access Address and Pin Multiplexing
The base address of accessing the I2C controller is the base address of the MISC low-speed device block plus an offset of 0x10000.
Note: The I2C module only supports access by 1 byte.
The physical address composition of the I2C module internal registers is as follows.
| Address bits | Composition | Note |
|---|---|---|
|
|
Reserved |
|
I2C controller number |
|
|
|
Reserved |
|
|
Internal registers address |
For I2C modules, the corresponding pins should be set to the corresponding functions when used. The pin settings related to I2C are described in Pin Multiplexing Configuration Register.
10.2. Description of I2C Controller Register
Frequency Division Latch Low-order Byte Register (PRERlo)
Offset: 0x00
Reset value: 0xff
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Store the lower |
Frequency Division Latch High-order Byte Register (PRERhi)
Offset: 0x01
Reset value: 0xff
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
RW |
Store the high |
Assuming that the value of the divider latch is Prescaler and the frequency of the I2C controller is 50MHz, if the clock frequency of the I2C bus is needed clock_s, then Prescaler should be equal to: 50M/(5*clock_s) - 1.
Control Register (CTR)
Offset: 0x02
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Module enable bit
|
|
|
|
R/W |
Interrupt enable bit
|
|
|
|
R/W |
Reserved |
Transport Data Register (TXR)
Offset: 0x03
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
W |
When transporting data, the data to be sent ( When transporting the address, the address of the I2C slave device is stored |
|
|
|
W |
When transporting data, stores the data to be sent ( When transporting the address, the read and write status is stored.
|
Receive Data Register (RXR)
Offset: 0x03
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R |
Store received data |
Command Control Register (CR)
Offset: 0x04
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
W |
Generate the |
|
|
|
W |
Generate the |
|
|
|
W |
Generate the read signal |
|
|
|
W |
Generate the write signal |
|
|
|
W |
Generate the response signal
|
|
|
|
W |
Reserved |
|
|
|
W |
Generate interrupt response signal.
Software writes |
State Register (SR)
Offset: 0x04
Reset value: 0x00
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R |
Receive response bit
|
|
|
|
R |
I2c bus busy flag bit
|
|
|
|
R |
When the I2C core loses control of the I2C bus, this bit is |
|
|
|
R |
Reserved |
|
|
|
R |
Indicate the process of transport
|
|
|
|
R |
Interrupt flag bit.
When one data transport is finished, or another device initiates data transport, this bit is |
11. PWM Controller
A four-way pulse width output/counter controller (PWM) is implemented in the bridge.
The four PWMs The four PWMs work and control in exactly the same way.
Each PWM pin can be used as either a pulse output signal or a pulse width measurement input signal.
The PMW controller clock is 50MHz, and the count and reference registers are 32-bit length.
11.1. Access Address and Pin Multiplexing
The base address of accessing the PWM controller is the base address of the MISC low-speed device block plus an offset of 0x20000.
Note: The PWM module only supports access by 4 bytes.
The physical address composition of the PWM controller internal registers is as follows.
| Address bits | Composition | Note |
|---|---|---|
|
|
Reserved |
|
PWM number |
|
|
|
Reserved |
|
|
Internal registers address |
For PMM modules, the corresponding pins should be set to the corresponding functions when used. The pin settings related to PMM are described in Pin Multiplexing Configuration Register.
11.2. Description of Registers
There are three registers per controller, which are described as follows.
| Name | Address | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Low pulse width register |
|
|
|
R/W |
Pulse period width register |
|
|
|
R/W |
Control register |
PWM Control Register Configuration
| Bit Field | Name | Read/Write | Reset Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
PWM enable bit
|
|
|
R/W |
|
Reserved |
|
|
R/W |
|
Pin pulse output enable control bit (active low).
When set to
|
|
|
R/W |
|
Single pulse control bit, valid for non-measurement mode
|
|
|
R/W |
|
Interrupt enable bit.
In the non-measurement mode, an interrupt is generated for every pulse period measured.
In the measurement mode, an interrupt is generated when the input pulse period is greater than
|
|
|
R/W |
|
Interrupt status bit.
Write
|
|
|
R/W |
|
Counter reset
|
|
|
R/W |
|
Measurement pulse enable
|
|
|
R/W |
|
Output invert enable, valid for non-measurement mode
|
|
|
R/W |
|
Anti dead zones function enable, valid for non-measurement mode
|
11.3. Description of Functions
11.3.1. Pulse Width Modulation Function
The low_buffer and full_buffer registers are used to configure the low level of the periodic signal and the length of the total period of the PWM output in the clock period of the PWM module (20ns), respectively.
For example, to generate a low pulse width of 50 times the PWM module clock period and a high pulse width of 90 times the PWM module clock period, you should configure the value 50 in the low_buffer and (50+90)=140 in the full_buffer.
The pulse width register value should be written before the CTRL control register.
Before writing a new number to the pulse width register, you should clear the EN bit in the control register and then set the EN bit to 1 after writing the new number.
If 0 is written to both buffer registers, the output is always low.
If writing 0 to low_buffer and 1 to full_buffer, the output is always high.
If the value written to low_buffer is not less than the value of full_buffer, the output is low.
11.3.2. Pulse Measurement Function
After setting the CTRL control register, the PWM continuously samples the input signal level.
When a down-jump of the input pulse signal is detected, the internal counter starts counting from 1, and when an up-jump is detected, the counter value is shifted to the low_buffer register and continues to accumulate, and when a down-jump is detected again, the counter value is shifted to the full_buffer register.
For example, if the input pulse is 50 times the low pulse width of the system clock and 90 times the high pulse width, the final value read in the low_buffer is 50, and the value read in the full_buffer register is (50+90)=140.
It should be noted that the pulse to be measured should be a periodic signal, and the pulse period should not exceed the range that the 32-bit counter can measure.
If there is a pulse with a pulse period longer than 0xFFFF_FFF9, the INT bit of the control register will be set to 1, indicating that the pulse to be measured is out of the measurement range.
11.3.3. Anti Dead Zones Function
Multiple PWMs are equipped with an anti dead zones function between them, which prevents multiple pulse outputs from jumping at the same time.
To use the anti dead zones function, the multiple PWMs of the anti dead zones function must be numbered from 0 and be consecutive, and their anti dead zones functions must all be enabled.
In other words, one of PWM0/1, PWM0/1/2 and PWM0/1/2/3 must be used when using the anti dead zones function.
For PWM_0, PWM_1, PWM_2, and PWM_3, their priority is 0> 1 > 2 > 3.
If they jump at the same time, PWM_1 will jump only after PWM_0 jumps (the lower priority signal is “erased” by one clock cycle), and so on.
This priority is fixed and cannot be changed.
A typical anti dead zones example is as follows (PWM_* is the output when the anti dead zones function is disabled, and PWM_*' is the output when the anti dead zones function is enabled).
12. Power Management Module (ACPI Support)
Bridge power management module provides system power management functions. It supports Advanced Configuration and Power Interface, Version 4.0a (ACPI) to provide the corresponding power management functions.
-
System hibernation and wake-up, support for ACPI S3 (suspend to RAM), ACPI S4 (suspend to disk), ACPI S5 (soft off), and support for power failure detection and automatic system recovery. It also supports multiple wake-up methods (USB, GMAC, power switch, etc.)
-
System clock control, module clock gating, multiple ways to adjust the frequency.
-
It integrates a watchdog with a maximum timing time of about
82s.
12.1. Access Address
The base address of accessing the power management module is the base address of the MISC low-speed device block plus an offset of 0x50000.
Note: The PWM module only supports access by 4 bytes.
The physical address composition of the ACPI module internal registers is as follows.
| Address bits | Composition | Note |
|---|---|---|
|
|
Reserved |
|
|
Internal registers address |
12.2. Power Level
G0/S0 |
Work all. The system works all in this mode |
|---|---|
|
Not supported at the moment |
|
Suspend to RAM (STR). Context saving to memory |
|
Suspend to Disk (STD). Save to hard disk, except wake-up circuit all power down |
|
Soft off. Only the wake-up circuit is powered on |
|
Mechanical off. All power supply failures |
12.3. Description of Registers
This section describes the power management related registers. The register voltage field indicates the voltage field to which this bit of the register belongs.
PMCON_SOC: SOC General PM Configuration Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W, RO |
|
Bit Field |
Description |
||
|
This bit indicates the current |
||
|
This bit indicates the power supply mode.
|
||
|
Reserved |
||
PMCON_RESUME : RESUME General PM Configuration Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W, RO, R/WC |
|
Bit Field |
Description |
||
|
Reserved |
||
|
Enables or disables the
If |
||
|
Used to control the duration of the
This field is |
||
|
Reserved |
||
|
If |
||
|
The system enters the G2/S5 state when a temperature trip occurs in the S0 state, and this bit is used to detect the logged event status after re-powering the system. |
||
|
Enable the temperature trip protection mechanism. |
||
|
Display status detection bit.
|
||
|
Reserved |
||
|
0: 1: |
||
|
When the system is in the S0 state, the PWROK signal becomes invalid and this bit is set to |
||
|
This bit does not affect the hardware function, PMON will set this bit to |
||
PMCON_RTC : RTC General PM Configuration Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W, R/WC |
|
Bit Field |
Description |
||
|
Reserved |
||
|
Controls whether the 0: 1: |
||
|
When the system enters a low-power state and is battery powered and
|
||
|
The 2 bits represent the minimum time interval between when the
|
||
|
The 2 bits represent the minimum time interval between when the
|
||
|
|
||
|
This bit is in the RTC domain and can only be reset by
|
||
|
This bit determines the action of the system after it enters the G3 state and the power is restored.
This bit will be set to |
||
PM1_STS : Power Management 1 Status Register
Address Offset |
Voltage Field |
Attribute |
|||
|
|
R/WC |
|||
Bit Field |
Description |
Voltage Field |
|||
|
Reserved |
||||
|
|
|
|||
|
|
|
|||
|
Reserved |
||||
|
|
|
|||
|
|
|
|||
|
Reserved |
||||
|
|
|
|||
|
Reserved |
||||
|
TMROF_STS (PM Timer Overflow Status) - R/WC
|
|
|||
PM1_EN: Power Management 1 Enable Register
Address Offset |
Voltage Field |
Attribute |
|||
|
|
R/W |
|||
Bit Field |
Description |
Voltage Field |
|||
|
Reserved |
||||
|
When this bit is set, no PCIE wake-up event is generated, but the value of this bit does not affect the value of |
|
|||
|
Reserved |
||||
|
RTC wake-up and interrupt enable. |
|
|||
|
Reserved |
||||
|
|
|
|||
|
Reserved |
||||
|
TMROF_EN (PM Timer Overflow Enable) - R/W If this bit is set, |
|
|||
PM1_CNT: Power Management 1 Control Register
Address Offset |
Voltage Field |
Attribute |
|||
|
RESUME/RTC/SOC |
R/W |
|||
Bit Field |
Description |
Voltage Field |
|||
|
Reserved |
||||
|
SLP_EN (Sleep Enable) - R/W Writing |
|
|||
|
This 3 bits indicate the hibernation state of the system.
|
|
|||
|
Reserved |
||||
|
Interrupt enable switch to enable the generation of interrupt signals for the power management controller. |
|
|||
PM1_TMR: Power Management 1 Timer
Address Offset |
Voltage Field |
Attribute |
|
|
|
RO |
|
Bit Field |
Description |
||
|
Reserved |
||
|
Counter counts with a period of |
||
GPE0_STS: General Purpose Event0 Status Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/WC |
|
Bit Field |
Description |
||
|
Reserved |
||
|
Only the bit
|
||
|
Reserved |
||
|
|
||
|
If |
||
|
|
||
|
|
||
|
|
||
|
Thermal warning is generated. |
||
|
CTA_STS - R/WC Thermal alert is generated. |
||
|
The |
||
|
Reserved |
||
GPE0_EN: General Purpose Event0 Enable Register
Address Offset |
Voltage Field |
Attribute |
|||
|
|
R/W |
|||
Bit Field |
Description |
Voltage Field |
|||
|
Reserved |
||||
|
|
||||
|
Reserved |
||||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
||||
|
|
||||
3 |
Enable THERMAL WARNING interrupt. |
||||
|
Enable THERMAL ALERT interrupt. |
||||
|
Enable PWRSWITCH_STS interrupt. |
||||
|
This bit sets the polarity of the |
||||
RST_CNT: Reset Control Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W |
|
Bit Field |
Description |
||
|
Reserved |
||
|
Watch dog function enable. |
||
|
Software writes this bit to reset the system. |
||
WD_SET : Watch Dog Set Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
WO |
|
Bit Field |
Description |
||
|
Reserved |
||
|
When |
||
WD_Timer: Watch Dog Timer Register
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W |
|
Bit Field |
Description |
||
|
The value of this register is the watch dog refill value, and the reset value is all |
||
GEN_RTC_1: General RTC Register 1
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W |
|
Bit Field |
Description |
||
|
RTC general purpose register. |
||
GEN_RTC_2: General RTC Register 2
Address Offset |
Voltage Field |
Attribute |
|
|
|
R/W |
|
Bit Field |
Description |
||
|
RTC general purpose register. |
||
13. RTC
The Real Time Clock (RTC) unit can be configured when the motherboard is powered up, and when the motherboard is powered down, the unit still operates and can run normally on the on-board battery power alone. The RTC unit operates with only a few microamps of current.
The RTC contains an oscillator, which in combination with an external 32.768KHZ crystal generates the operating clock.
This clock is used for time information maintenance and is used to maintain time information and to generate various timing and counting interrupts.
The RTC module contains two counters, the TOY (Time of Year) counter and the RTC counter.
The TOY counter counts in years, months, hours, minutes and seconds with an accuracy of 0.1s.
The RTC counter counts at 32.768KHz and is 32-bit length.
13.1. Access Address
The base address of accessing the RTC module is the base address of the MISC low-speed device block plus an offset of 0x50100.
Note: The RTC module only supports access by 4 bytes.
The physical address composition of the RTC module internal registers is as follows.
| Address bits | Composition | Note |
|---|---|---|
|
|
Reserved |
|
|
Reserved |
|
|
Internal registers address |
13.2. Description of Registers
| Name | Offset address | Length | Read/Write | Description |
|---|---|---|---|---|
|
|
|
R/W |
Software must initialize it to |
|
|
|
WO |
TOY low 32 bits input |
|
|
|
WO |
TOY high 32 bits input |
|
|
|
RO |
TOY low 32 bits output |
|
|
|
RO |
TOY high 32 bits output |
|
|
|
R/W |
TOY timer interrupt 0 |
|
|
|
R/W |
TOY timer interrupt 1 |
|
|
|
R/W |
TOY timer interrupt 2 |
|
|
|
R/W |
TOY and RTC control registers Software must initialize them |
|
|
|
R/W |
Software must initialize it to |
|
|
|
WO |
RTC timer counter input |
|
|
|
RO |
RTC timer counter output |
|
|
|
R/W |
RTC clock timer interrupt 0 |
|
|
|
R/W |
RTC clock timer interrupt 1 |
|
|
|
R/W |
RTC clock timer interrupt 2 |
13.2.1. SYS_TOYWRITE0
Address Offset: 24-27h
Attribute: WO
Default value: N/A
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
Month, range |
|
|
WO |
Day, range |
|
|
WO |
Hour, range |
|
|
WO |
Minute, range |
|
|
WO |
Second, range |
|
|
WO |
|
13.2.2. SYS_TOYWRITE1
Address Offset: 28-2Bh
Attribute: WO
Default value: N/A
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
Year, range |
13.2.3. SYS_TOYREAD0
Address Offset: 2C-2Fh
Attribute: RO
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Month, range |
|
|
RO |
Day, range |
|
|
RO |
Hour, range |
|
|
RO |
Minute, range |
|
|
RO |
Second, range |
|
|
RO |
|
13.2.4. SYS_TOYREAD1
Address Offset: 30-33h
Attribute: RO
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Year, range |
13.2.5. SYS_TOYMATCH0
Address Offset: 34-37h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Year, range |
|
|
R/W |
Month, range |
|
|
R/W |
Day, range |
|
|
R/W |
Hour, range |
|
|
R/W |
Minute, range |
|
|
R/W |
Second, range |
13.2.6. SYS_TOYMATCH1
Address Offset: 38-3Bh
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Year, range |
|
|
R/W |
Month, range |
|
|
R/W |
Day, range |
|
|
R/W |
Hour, range |
|
|
R/W |
Minute, range |
|
|
R/W |
Second, range |
13.2.7. SYS_TOYMATCH2
Address Offset: 3C-3Fh
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Year, range |
|
|
R/W |
Month, range |
|
|
R/W |
Day, range |
|
|
R/W |
Hour, range |
|
|
R/W |
Minute, range |
|
|
R/W |
Second, range |
13.2.8. SYS_RTCCTRL
Address Offset: 40-43h
Attribute: RO, R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved |
|
|
RO |
|
|
|
RO |
Reserved |
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
Reserved |
|
|
R/W |
RTC enable (active high). Needs to be initialized to |
|
|
RO |
Reserved |
|
|
R/W |
TOY enable (active high). Needs to be initialized to |
|
|
RO |
Reserved |
|
|
R/W |
|
|
|
RO |
Reserved |
|
|
RO |
|
|
|
RO |
Reserved |
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
|
|
RO |
|
13.2.9. SYS_RTCWRITE
Address Offset: 64-67h
Attribute: WO
Default value: N/A
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
RTC counter input register |
13.2.10. SYS_RTCREAD
Address Offset: 68-6Bh
Attribute: RO
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
RTC counter output register |
13.2.11. SYS_RTCMATCH0
Address Offset: 6C-6Fh
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
RTC timer comparison register 0 |
13.2.12. SYS_RTCMATCH1
Address Offset: 70-73h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
RTC timer comparison register 1 |
13.2.13. SYS_RTCMATCH2
Address Offset: 74-77h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
RTC timer comparison register 2 |
14. GPIO
The bridge chip has 57 GPIO pins, GPIO00 is a dedicated GPIO pin, and the remaining 56 are multiplexed with other functions.
Each GPIO pin is controlled by a set of control registers, including: GPIO direction control (GPIO_OEN), GPIO output (GPIO_O), GPIO input (GPIO_I), and GPIO input interrupt enable control (GPIO_INT_EN).
| Register | Size (bit) | Description |
|---|---|---|
|
|
GPIO output enable (active low). |
|
|
GPIO output. |
|
|
GPIO input. |
|
|
GPIO interrupt enable. |
14.1. Access Address
The base address of accessing the GPIO module is the base address of the MISC low-speed device block plus an offset of 0x60000.
Note: The GPIO module only supports access by 1 byte.
The bridge chip provides two ways to control the GPIO pins. One is to control each GPIO pin by bit and the other is to control each GPIO pin by byte. The bridge chip does this by providing two address spaces to map the GPIO control registers. One is a per-bit mapping and the other is a per-byte indexing of each bit of the control register. Correspondingly, the GPIO internal address space is divided into two parts.
The latter way is recommended for the GPIO controller pins.
The physical address composition of the GPIO module internal registers is as follows.
| Address space | Description |
|---|---|
|
Address of byte control register |
|
Address of bit control register |
| Address Offset | Register | Size (bit) | Description |
|---|---|---|---|
|
|
|
GPIO output enable (active low). Each bit controls one GPIO pin. |
|
|
|
GPIO output. Each bit controls one GPIO pin. |
|
|
|
GPIO input. Each bit controls one GPIO pin. |
|
|
|
GPIO interrupt enable. Each bit controls one GPIO pin. |
| Address Offset | Register | Size (bit) | Description |
|---|---|---|---|
|
|
|
GPIO output enable (active low).
Each byte controls one GPIO pin, bit |
|
|
|
GPIO output.
Each byte controls one GPIO pin, bit |
|
|
|
GPIO input.
Each byte controls one GPIO pin, bit |
|
|
|
GPIO interrupt enable.
Each byte controls one GPIO pin, bit |
For example, the output input direction of GPIO03 can be controlled either by bit[3] with offset address 0x0 (taking care not to affect other bits) or by a byte with offset address 0x803 (only bit[0] is valid).
14.2. Description of Registers
GPIO Direction Control
Address Offset: 00-03h
Attribute: R/W
Default value: FFFFFFF0h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Corresponds to the direction control of
|
Address Offset: 04-07h
Attribute: R/W
Default value: FFFFFFFFh
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved. |
|
|
R/W |
Corresponds to the direction control of
|
GPIO Output
Address Offset: 00-03h
Attribute: R/W
Default value: 0000000Fh
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Corresponds to the output of |
Address Offset: 04-07h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved. |
|
|
R/W |
Corresponds to the output of |
GPIO Input
Address Offset: 00-03h
Attribute: RO
Default value: N/A
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Corresponds to the input of |
Address Offset: 04-07h
Attribute: RO
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved. |
|
|
RO |
Corresponds to the input of |
GPIO Interrupt Enable
Address Offset: 00-03h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Corresponds to the interrupt enable of
|
Address Offset: 04-07h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
Reserved. |
|
|
R/W |
Corresponds to the interrupt enable of
|
15. GMAC Controller (D3:F0, D3:F1)
The bridge integrates two GMAC controllers, which have the same functions.
Note: See Notes on the Use of the Software for software enablement of 64-bit DMA for the GMAC controllers.
15.1. GMAC Configuration Register (D3:F0, D3:F1)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
|
|
Vendor ID |
|
RO |
|
|
Device ID |
|
RO |
|
|
PCI Command |
|
R/W, RO |
|
|
Revision ID |
|
RO |
|
|
Programming Interface |
|
RO |
|
|
Sub Class Code |
|
RO |
|
|
Base Class Code |
|
RO |
|
|
Cache Line Size |
|
RO |
|
|
Header Type |
|
RO |
|
|
Control Block Base Address Register |
|
R/W, RO |
|
|
Subsystem Vendor ID |
|
RO |
|
|
Subsystem Identification |
|
RO |
|
|
Interrupt Line |
|
R/W |
|
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (GMAC - D3:F0, D3:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the GMAC control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the GMAC control register. |
|
|
RO |
The address space size of GMAC control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the GMAC control register. |
16. USB Controller (D4:F0/1, D5:F0/1)
The bridge contains two USB controllers, each containing three ports.
The USB ports of the bridge have the following features.
-
Compatible with USB Rev 1.1, USB Rev 2.0 protocols
-
Compatible with OHCI Rev 1.0, EHCI Rev 1.0 protocols
-
Supports LS (Low Speed), FS (Full Speed) and HS (High Speed) USB devices
-
Works in Host mode, OTG mode is not supported
Each USB controller module of the bridge includes an EHCI controller and an OHCI controller, with each EHCI controller and OHCI controller supporting 3 ports. The EHCI controller is used by default, and control is transferred to the OHCI controller only when the hooked up device is a full-speed or low-speed device. When a full-speed or low-speed device is unplugged, control is returned to the EHCI controller.
Note: The Memory Space Enable control for the OHCI and EHCI device headers of USB devices requires special handling, see Notes on the Use of the Software.
16.1. EHCI Controller
16.1.1. EHCI Configuration Register (D4:F1, D5:F1)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (USB EHCI - D4:F1, D5:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the USB EHCI control registers is enabled.
In rev. 00, this bit controls the |
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the EHCI controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the EHCI control register. |
|
|
RO |
The address space size of EHCI control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the high 32-bit address of the base address allocated to the EHCI control register. |
The bridge’s USB host controller is compatible with the EHCI Rev 1.0 protocol. Refer to the Enhanced Host Controller Interface Rev 1.0 Specification for details of the Capability register and Operational register.
16.2. OHCI Controller
16.2.1. OHCI Configuration Register (D4:F0, D5:F0)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (USB OHCI - D4:F0, D5:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the USB OHCI control registers is enabled.
In rev. 00, this bit controls the Memory Space Enable of the EHCI.
The |
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the OHCI controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the OHCI control register. |
|
|
RO |
The address space size of OHCI control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the high 32-bit address of the base address allocated to the OHCI control register. |
The bridge’s USB host controller is compatible with the OHCI Rev 1.0 protocol. Refer to the Open Host Controller Interface Rev 1.0 Specification for details of the operational registers.
17. Graphics Processor (D6:F0)
17.1. GPU Configuration Register (D6:F0)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
18h-1Fh |
|
Graphic Memory Base Address Register |
|
R/W, RO |
27h-20h |
|
Reserved Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (GPU - D6:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the GPU control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the low address of the base address allocated to the GPU control register. |
|
|
RO |
The address space size of the GPU control registers is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the high 32-bit address of the base address allocated to the GPU control register. |
GMEM_BAR - Video Memory Base Address Register
This register is used to configure the base address of the video memory.
Address Offset: 18-1Bh
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low bit of the base address allocated to the video memory. |
|
|
RO |
The memory size is configured by the BIOS.
The maximum is not more than |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 1C-1Fh
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address allocated to the base address of the video memory. |
RSV_BAR - Reserved Window Base Address Register
This register is used to configure the base address of the reserved registers of the GPU controller.
Address Offset: 20-23h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the GPU reserved register. |
|
|
RO |
The address space size of the GPU reserved registers is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 24-27h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the GPU reserved register. |
17.2. DDR3 Memory Interface
The bridge chip’s integrated memory interface complies with the DDR3 SDRAM standard (JESD79-3).
The bridge supports 1 chip select, 16 row addresses, 15 column addresses, and 3 logical body addresses.
The bridge chip’s memory controller has the following characteristics.
-
Full-flow operation of commands, read and write data on the interface
-
Memory command merging and sorting to improve the overall bandwidth
-
Basic parameters of memory devices can be modified
-
Supports
133-667MHzclock frequency
Access Address
The DDR3 memory controller consists of two address spaces: the memory space for video memory controller configuration register and the memory space for the video memory.
These two address spaces share the same address space (the video memory address space, the address space allocated to GMEM_BAR).
The final access to the memory address space is determined by the parameter disable_gmem_confspace — bit 3 of general configuration register 0 of the bridge configuration register addr_0x420[3].
When the configuration parameter disable_gmem_confspace = 0, all accesses to the memory are configuration register accesses.
When the configuration parameter disable_gmem_confspace = 1, the accesses to the memory are normal memory read and write accesses.
18. Display Controller (D6:F1)
The features supported by the display controller of the bridge include the following.
-
Dual DVO interface displays
-
Each display supports up to
1920x1080@60Hz -
Two hardware cursors modes: Monochrome, ARGB8888
-
Four color depths: RGB444, RGB555, RGB565, RGB888
-
Output dithering and gamma correction
-
Switchable dual routability frame buffer
-
Interrupt and soft reset
18.1. DC Configuration Register (D6:F1)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (DC - D6:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the DC control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the GMAC controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address assigned to the DC control register. |
|
|
RO |
The address space size of DC control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the high 32-bit address of the base address assigned to the DC control register. |
18.2. DC Control Register
18.2.1. Display Detection Register
The 7A bridge contains two sets of I2C bus pins specifically for display detection.
These two sets of I2C bus pins need to be emulated by software using GPIO pins.
These two sets of GPIO pins differ from the GPIO pins in the MISC in that their control registers are placed in the control register space of the DC.
The I2C bus of DVO0 is controlled by bit[1:0] of the GPIO register, and the I2C bus of DVO1 is controlled by bit[3:2] of the GPIO register.
The correspondence between I2C pins and GPIO registers is shown in the following table.
| Pin Name | GPIO control bit |
|---|---|
|
|
|
|
|
|
|
|
Each GPIO control bit is controlled by three registers. The addresses of the GPIO control registers are shown in the following table.
Register Name |
Address Offset |
Read/Write |
Description |
Reset Value |
|||||
|
|
WO |
Output register |
|
|||||
|
|
RO |
Input register |
N/A |
|||||
|
|
R/W |
GPIO direction control register |
|
|||||
|
Bit |
Description |
Initial Value |
||||||
|
|
Control the output value of the |
|
||||||
|
|
Control the output value of the |
|
||||||
|
|
Control the output value of the |
|
||||||
|
|
Control the output value of the |
|
||||||
|
Bit |
Description |
Initial Value |
||||||
|
|
Control the input value of the |
N/A |
||||||
|
|
Control the input value of the |
N/A |
||||||
|
|
Control the input value of the |
N/A |
||||||
|
|
Control the input value of the |
N/A |
||||||
|
Bit |
Description |
Initial Value |
||||||
|
|
Control the direction of the |
|
||||||
|
|
Control the direction of the |
|
||||||
|
|
Control the direction of the |
|
||||||
|
|
Control the direction of the |
|
||||||
19. HDA Controller (D7:F0)
The HDA controller is compatible with High Definition Audio Specification Revision 1.0a.
See PLL1 Configuration Register for HDA-related pin setup registers.
19.1. HDA Configuration Register (D7:F0)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note:
-
The HDA configuration header is only visible when the relevant pin is configured for HDA mode.
-
Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (HDA - D7:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the HDA control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the HDA controller’s control registers.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
Software writes to this register field the low address of the base address assigned to the HDA control register. |
|
|
RO |
The HDA control register has an address space size of |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address assigned to the base address of the HDA control register. |
19.2. Description of HDA Control Register
The HDA control registers are designed in full accordance with the HD audio Rev 1.0 specification. The following table lists the main register parameters.[1] Refer to the HD audio Rev 1.0 manual for details.
20. AC97 Controller (D7:F1)
20.1. AC97 Configuration Register (D7:F1)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note:
-
The AC97 configuration header is only visible when the relevant pin is configured for AC97 mode.
-
Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (AC97 - D7:F1)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the AC97 control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the AC97 control register.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the AC97 control register. |
|
|
RO |
The address space size of AC97 control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the AC97 control register. |
20.2. AC97 Controller Register
| Address Offset | Abbreviation | Description | Default Value | Read/Write |
|---|---|---|---|---|
|
|
Vendor ID |
|
RO |
|
|
Device ID |
|
RO |
|
|
PCI Command |
|
R/W, RO |
|
|
Revision ID |
|
RO |
|
|
Programming Interface |
|
RO |
|
|
Sub Class Code |
|
RO |
|
|
Base Class Code |
|
RO |
|
|
Cache Line Size |
|
RO |
|
|
Header Type |
|
RO |
|
|
Control Block Base Address Register |
|
R/W, RO |
|
|
Subsystem Vendor ID |
|
RO |
|
|
Subsystem Identification |
|
RO |
|
|
Interrupt Line |
|
R/W |
|
|
Interrupt Pin |
|
RO |
CSR Register
Offset address: 0x00
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
Reserved |
|
RO |
Reserved. |
|
RESUME |
|
R/W |
Hanging. Read this bit to return the current state of the AC97 subsystem.
Writing |
|
RST_FORCE |
|
W |
AC97 cold boot. Writing |
OCC Register
Offset address: 0x04
Reset value: 0x00004141
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
Reserved |
|
R/W |
Reserved. |
|
Reserved |
|
R/W |
Reserved. |
|
OC1_CFG_R |
|
R/W |
Output channel 1: Right channel configuration. |
|
OC0_CFG_L |
|
R/W |
Output channel 0: Left channel configuration. |
ICC Register
Offset address: 0x10
Reset value: 0x00410000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
Reserved |
|
R/W |
Reserved. |
|
IC_CFG_MIC |
|
R/W |
Input channel 2: MIC channel configuration. |
|
Reserved |
|
R/W |
Reserved. |
|
Reserved |
|
R/W |
Reserved. |
| Bit Field | Name | Length | Read/Write | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Reserved |
|
R/W |
Reserved. |
|||||||||||||||
|
DMA_EN |
|
R/W |
DMA enable.
|
|||||||||||||||
|
FIFO_THRES |
|
R/W |
FIFO threshold
|
|||||||||||||||
|
SW |
|
R/W |
Number of sampling bits
|
|||||||||||||||
|
VSR |
|
R/W |
Sampling rate
|
|||||||||||||||
|
CH_EN |
|
R/W |
Channel enable
|
Codec Register Access Command
Offset address: 0x110
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
CODEC_WR |
|
R/W |
Read/write selection
|
|
Reserved |
|
R |
Reserved. |
|
CODEC_ADR |
|
R/W |
Codec register address |
|
CODEC_DAT |
|
R/W |
Codec register data |
Interrupt Status Register/Interrupt Mask Register
Offset address: 0x54/510
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
IC_FULL |
|
R/W |
Input channel 2: FIFO full |
|
IC_TH_INT |
|
R/W |
Input channel 2: FIFO reaches threshold |
|
Reserved |
|
R/W |
Reserved. |
|
OC1_FULL |
|
R/W |
Output channel 1: FIFO full |
|
OC1_EMPTY |
|
R/W |
Output channel 1: FIFO empty |
|
OC1_ TH_INT |
|
R/W |
Output channel 1: FIFO reaches threshold |
|
OC0_FULL |
|
R/W |
Output channel 0: FIFO full |
|
OC0_EMPTY |
|
R/W |
Output channel 0: FIFO empty |
|
OC0_ TH_INT |
|
R/W |
Output channel 0: FIFO reaches threshold |
|
CW_DONE |
|
R/W |
Codec register write complete |
|
CR_DONE |
|
R/W |
Codec register read complete |
Interrupt Status/Clear Register
Offset address: 0x5c
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
INT_CLR |
|
RO |
After masking the interrupt status register, a read of this register will clear all interrupt status in register |
OC Interrupt Clear Register
Offset address: 0x60
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
INT_OC_CLR |
|
RO |
A read operation of this register will clear the |
IC Interrupt Clear Register
Offset address: 0x64
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
INT_IC_CLR |
|
RO |
A read operation of this register will clear the |
CODEC WRITE Interrupt Clear Register
Offset address: 0x610
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
INT_CW_CLR |
|
RO |
A read operation of this register will clear the |
CODEC READ Interrupt Clear Register
Offset address: 0x6c
Reset value: 00000000h
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
INT_CR_CLR |
|
RO |
A read operation of this register will clear the |
DMA Command Register
This register is used to control the internal DMA controller of the AC97. The DMA controller is described in detail in the following section.
Offset address: 0x100
Reset value: 00000000h
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
ask_addr |
R/W |
|
|
Reserved |
R/W |
Reserved. |
|
dma_stop |
R/W |
Stop DMA operation. The DMA controller stops when it has completed reading or writing the current data. |
|
dma_start |
R/W |
Start DMA operation.
The DMA controller reads the descriptor address ( |
|
ask_valid |
R/W |
The DMA working register is written back to the memory pointed to by ( |
|
Reserved |
R/W |
Reserved. |
|
dma_64bit |
R/W |
DMA controller 64-bit address support. |
20.3. DMA Controller
20.3.1. Description of DMA Controller Structure
The bridge contains 2 DMA controllers for data migration between memory and AC97, which can save resources and improve the efficiency of system data transfer. This saves resources and improves the efficiency of system data transfer.
The process of transporting data by DMA consists of three stages.
-
Pre-processing before transport: The CPU configures the registers related to the DMA descriptor.
-
Data transport: done automatically under the control of the DMA controller.
-
End-of-transport processing: sending an interrupt request.
This DMA controller is limited to data handling in words (4-byte).
The DMA controller supports 64-bit address space, which is mainly controlled by dma_64bit.
When this bit is set to 1, it means that the DMA controller works in 64-bit address space, and vice versa for 32-bit address space.
In 64-bit address mode, it is necessary to extend DMA_ORDER_ADDR and DMA_SADDR to 64-bit registers.
20.3.2. DMA Descriptor
DMA_ORDER_ADDR_LOW
Offset address: 0x0
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_order_addr |
|
R/W |
Memory internal next descriptor address register (low 32 bits). |
|
Dma_order_en |
|
R/W |
Whether the descriptor is a valid signal. |
Description: Store the address of the next DMA descriptor.
dma_order_en is the enable bit of the next DMA descriptor.
If this bit is 1, the next descriptor is valid; if this bit is 0, the next descriptor is invalid and no operation is performed.
When the DMA descriptor is configured, this register holds the address of the next descriptor. After the DMA operation is performed, the dma_order_en signal is used to determine whether to start the next DMA operation.
In 64-bit address mode, this register stores the low 32-bit address.
DMA_SADDR
Offset address: 0x4
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_saddr |
|
R/W |
System memory address for DMA operations (low 32 bits). |
Description: DMA operations are divided into Memory Read and Memory Write. Memory Read: reads data from memory, saves it in the DMA controller’s cache, and then writes it to the AC97 device; this register specifies the address of the read memory. Memory Write: Read data from AC97 device is saved in the DMA cache, and when the data in the DMA cache exceeds a certain number, it is written to the memory, and this register specifies the address of the write memory. In 64-bit address mode, this register stores the low 32-bit address.
DMA_DADDR
Offset address: 0x8
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
AC97_wr_en |
|
R/W |
AC97 write enable.
|
|
AC97_mode |
|
R/W |
|
|
AC97_wr_mode |
|
R/W |
AC97 write mode.
|
|
dma_daddr |
|
R/W |
AC97 device address for DMA operation. |
DMA_LENGTH
Offset address: 0xc
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_length |
|
R/W |
Transport data length register. |
Description: Represents the length of a piece of content to be carried, in words.
When the length of the word has been carried, the next step is started, i.e. the next loop.
When a new loop is started, the length of data is carried again.
When step becomes 1, the single DMA descriptor operation ends and the next descriptor is read.
DMA_STEP_LENGTH
Offset address: 0x10
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_step_length |
|
R/W |
Data transport interval length register. |
Description: The length of the interval between two blocks of memory data being carried, the interval between the end address of the previous step and the start address of the next step.
DMA_STEP_TIMES
Offset address: 0x14
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_step_times |
|
R/W |
Data transport cycle count register. |
Description: The number of cycles indicates the number of blocks to be carried in a single DMA operation.
If you want to carry only one consecutive block, the value of the cycle count register can be assigned to 1.
DMA_CMD
Offset address: 0x18
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
Dma_cmd |
|
R/W |
Source and destination address generation method. |
|
dma_r_w |
|
R/W |
DMA operation type, |
|
dma_write_state |
|
R/W |
DMA write data status. |
|
dma_read_state |
|
R/W |
DMA read data status. |
|
dma_trans_over |
|
R/W |
The DMA has executed all the configured descriptor operations. |
|
dma_single_trans_over |
|
R/W |
The DMA has executed a descriptor operation. |
|
dma_int |
|
R/W |
DMA interrupt signal. |
|
dma_int_mask |
|
R/W |
Whether DMA interrupts are masked. |
Description: dma_single_trans_over=1 means the end of one DMA operation, when length=0 and step_times=1, the descriptor of the next DMA operation will be taken.
The descriptor address of the next DMA operation is stored in the DMA_ORDER_ADDR register.
If dma_order_en=0 in the DMA_ORDER_ADDR register, then dma_trans_over=1 and the whole dma operation is finished and there are no new descriptors to read.
If dma_order_en=1, then dma_trans_over is set to 0 and the next dma descriptor is read.
dma_int is the interrupt of the DMA, which occurs after a configured DMA operation if there is no interrupt mask.
The CPU can set it low directly after processing the interrupt, or it can wait until the DMA makes its next transfer.
dma_int_mask is the interrupt mask for the corresponding dma_int.
dma_read_state describes the current read state of the DMA.
dma_write_state describes the current write state of the DMA.
The DMA write state (WRITE_STATE[3:0]) describes that the DMA includes the following write states.
| Write_state | [3:0] | Description |
|---|---|---|
|
|
Write state is in idle state |
|
|
Dma determines that it needs to perform a read device write memory operation and initiates a write memory request, but the memory is not ready to respond to the request, so dma keeps waiting for a response from the memory |
|
|
Memory has received a dma write request, but has not yet finished executing the write operation |
|
|
The memory receives the dma write request and completes the write operation, at which point the dma is in the write memory operation complete state |
|
|
Dma sends a request to write the dma status register back to memory and waits for memory to receive the request |
|
|
Memory receives a write dma status request, but the operation is not yet complete |
|
|
Memory completes write dma status operation |
|
|
Dma completes a length length operation (i.e. completes a step) |
The DMA read state (READ_STATE[3:0]) describes that the DMA includes the following read states.
| Read_state | [3:0] | Description |
|---|---|---|
|
|
Read state is in idle state |
|
|
After receiving the start signal to start the dma operation, enter the ready state and start reading the descriptor |
|
|
Issue a read descriptor request to memory and wait for a memory answer |
|
|
Memory receives a read descriptor request and is performing a read operation |
|
|
Memory read out dma descriptor |
|
|
Dma sends a read data request to memory and waits for a memory answer |
|
|
Memory receives dma read data request and is performing read data operation |
|
|
Memory completes a read data request from dma |
|
|
Dma enters read device status |
|
|
The device returns read data, ending the read device request |
|
|
End a step operation, step times minus |
DMA_ORDER_ADDR_HIGH
Offset address: 0x20
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_order_addr |
|
R/W |
Memory internal next descriptor address register (high 32 bits) |
DMA_SADDR_HIGH
Offset address: 0x24
Reset value: 0x00000000
| Bit Field | Name | Length | Read/Write | Description |
|---|---|---|---|---|
|
dma_saddr |
|
R/W |
Memory address for DMA operation (high 32 bits) |
21. SATA Controller (D8:F0/1/2)
The features of SATA are as follows.
-
Supports SATA Generation 1 at 1.
5Gbpsand SATA Generation 2 at3Gbps -
Compatible with Serial ATA 2.6 specification and AHCI 1.1 specification
21.1. SATA Configuration Register (D8:F0/1/2)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (SATA - D8:F0/1/2)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the SATA control registers is enabled.
|
|
|
RO |
Reserved. |
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the SATA controller.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the SATA control register. |
|
|
RO |
The address space size of SATA control register is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the SATA control register. |
21.2. Description of SATA Control Register
The base address of SATA is given by BAR0 of SATA and the register definition is identical to the protocol standard definition.
| Address Offset | Length | Name | Description |
|---|---|---|---|
|
|
|
HBA characteristic register |
|
|
|
Global HBA control register |
|
|
|
Interrupt status register |
|
|
|
Port register |
|
|
|
AHCI version register |
|
|
|
Command completion merge control register |
|
|
|
Command completion merge port register |
|
|
|
HBA characteristic expansion register |
|
|
|
BIST active FIS |
|
|
|
BIST control register |
|
|
|
BIST FIS count register |
|
|
|
BIST status register |
|
|
|
BIST double word error count register |
|
|
|
OOB register |
|
|
|
|
|
|
|
Global parameter register 1 |
|
|
|
Global parameter register 2 |
|
|
|
Port parameter register |
|
|
|
Test register |
|
|
|
Version register |
|
|
|
ID register |
|
|
|
Command list base address low 32 bits |
|
|
|
Command list base address high 32 bits |
|
|
|
FIS base address low 32 bits |
|
|
|
FIS base address high 32 bits |
|
|
|
Interrupt status register |
|
|
|
Interrupt enable register |
|
|
|
Command register |
|
|
|
Task file data register |
|
|
|
Signature register |
|
|
|
SATA status register |
|
|
|
SATA control register |
|
|
|
SATA error register |
|
|
|
SATA active register |
|
|
|
Command send register |
|
|
|
SATA command notification register |
|
|
|
DMA control register |
|
|
|
PHY control register |
|
|
|
PHY status register |
|
|
|
Command list base address low 32 bits |
|
|
|
Command list base address high 32 bits |
|
|
|
FIS base address low 32 bits |
|
|
|
FIS base address high 32 bits |
|
|
|
Interrupt status register |
|
|
|
Interrupt enable register |
|
|
|
Command register |
|
|
|
Task file data register |
|
|
|
Signature register |
|
|
|
SATA status register |
|
|
|
SATA control register |
|
|
|
SATA error register |
|
|
|
SATA active register |
|
|
|
Command send register |
|
|
|
SATA command notification register |
|
|
|
DMA control register |
|
|
|
PHY control register |
|
|
|
PHY status register |
22. PCIE Controller (D9:F0, D10:F0, D11:F0, D12:F0, D13:F0, D14:F0, D15:F0, D16:F0, D17:F0, D18:F0, D19:F0, D20:F0)
The PCIEs of the bridge chip are divided into 5 groups: PCIE_F0, PCIE_F1, PCIE_H, PCIE_G0, PCIE_G1, with a total of 32 lanes.
Each group of PCIE interfaces has its own corresponding control port.
The bridge contains 12 PCIE control ports (ports), namely port 0, port 1, port 2, port 3 of PCIE_F0, port 0, port 1 of PCIE_F1, port 0, port 1 of PCIE_G0, port 0, port 1 of PCIE_G1, port 0, port 1 of PCIE_H, port 1 of PCIE_H.
Each port corresponds to a PCIE controller, and each PCIE controller contains a TYPE1 type PCI configuration header.
PCIE_F0 includes 4 lanes and can be used as one x4 PCIE or 4 x1 PCIEs.
Among them, port 0 controls lane0 in non x4 mode, port 0 controls lane0, and lane0-3 in x4 mode.
In non-x4 mode, port 1 controls lane1, port In non-x4 mode, port 1 controls lane1, port 2 controls lane2, and port 3 controls lane3.
PCIE_F1 includes 4 lanes, which can be used as one x4 PCIE or 2 x1 PCIEs.
Among them, port 0 controls lane0 in non lane0 in non-x4 mode and lane0-3 in x4 mode.
In non-x4 mode, port 1 controls lane1, lane2 and lane3 are not available.
PCIE_H includes 8 lanes and can be used as one x8 PCIE or 2 x4 PCIEs.
Among them, port 0 controls lane0-3 in non port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode.
In non-x8 mode, port 1 controls lane4-7.
PCIE_G0 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs.
Among them, port 0 controls lane4-7 in Port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode.
In non-x8 mode, port 1 controls lane4-7.
PCIE_G1 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs.
Among them, port 0 controls lane4-7 in port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode.
In non-x8 mode, port 1 controls lane4-7.
The PCIE controller of the bridge chip can be used only as RC, not as EP.
The configuration methods supported by PCIE and the corresponding control ports are shown in the tables below.
lane0 |
lane1 |
lane2 |
lane3 |
x4 (P0) |
|||
x1 (P0) |
x1 (P1) |
x1 (P2) |
x1 (P3) |
lane0 |
lane1 |
lane2 |
lane3 |
x4 (P0) |
|||
x1 (P0) |
x1 (P1) |
||
lane0 |
lane1 |
lane2 |
lane3 |
lane4 |
lane5 |
lane6 |
lane7 |
x8 (P0) |
|||||||
x4 (P0) |
x4 (P1) |
||||||
22.1. PCI Configuration Register
The following table lists the configuration header defaults for PCIE ports, the Device ID may be different for different ports, all other fields are the same.
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
See description of registers |
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
06h-07h |
|
PCI Status |
|
RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Dh |
|
Primary Latency Timer |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Block Base Address Register |
|
R/W, RO |
18h |
|
Primary Bus Number |
|
R/W |
19h |
|
Secondary Bus Number |
|
R/W |
1Ah |
|
Subordinate Bus Number |
|
R/W |
1Bh |
|
Secondary Latency Timer |
|
RO |
1Ch |
|
I/O Base |
|
R/W |
1Dh |
|
I/O Limit |
|
R/W |
1Eh-1Fh |
|
Secondary Status |
|
RO |
20h-21h |
|
Memory Base |
|
R/W |
22h-23h |
|
Memory Limit |
|
R/W |
25h-24h |
|
Prefetchable Memory Base |
|
R/W |
27h-26h |
|
Prefetchable Memory Limit |
|
R/W |
28h-2Bh |
|
Prefetchable Memory Base Upper 32 Bits |
|
R/W |
2Ch-2Fh |
|
Prefetchable Memory Limit Upper 32 Bits |
|
R/W |
30h-31h |
|
I/O Base Upper 16 Bits |
|
R/W |
32h-33h |
|
I/O Limit Upper 16 Bits |
|
R/W |
34h |
|
Capabilities Pointer |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
3Eh-3Fh |
|
Bridge Control Register |
|
R/W |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
DID - Device Identity Register (PCIE)
Address Offset: 02-03h
Attribute: RO
Default value: See description
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
PCIE device identity register. The corresponding DID of each PCIE port is shown in the following table. |
| PCI Device Number | Description | Device Identity Register |
|---|---|---|
|
|
|
|
|
|
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Note:
-
The correct value of the subclass code for all PCIE controllers integrated in the bridge should be 0x04 for the PCI-to-PCI bridge, but this bridge incorrectly implements this value as 0x00 (for the Host bridge). The software needs to ignore this bit field and still handle the bridge-integrated PCIE controllers as PCI-to-PCI bridges, see Notes on the Use of the Software.
-
Only one device (Device 0) can be mounted on the bus below all PCIE controllers integrated in the bridge, but when the software scans the PCIE bus for non-Device 0 devices, this PCIE controller will return the information of Device 0, causing Device 0 to be discovered repeatedly. Therefore, the software must not actively scan for non-Device 0 devices below the PCIE controller, see Notes on the Use of the Software.
22.2. Address Space Division
The PCIE controller in the bridge has a standard PCIE configuration header, so the internal registers of the PCIE controller and the address space of its downstream devices are managed by the information in its configuration header. The address-related registers in the configuration header are determined during the PCI device scan.
Because the bridge’s PCIE controller can only operate in RC mode, its configuration header is of type TYPE1.
Each PCIE port acts as a separate device in the bridge slice, and each port contains a PCIE configuration header. When the PCIE is operating in X4 mode, the port software for the other X1 is not visible, and the other X1 ports are only accessible when the PCIE is operating in X1 mode.
For each PCIE port, the address space can be divided into the following parts.
Configuration header address space: This part of the space corresponds to the configuration header of the PCIE and is accessed through configuration requests up to 4KB.
See Access Address of the PCI Configuration for accessing address space above 256B.
Configuration Access Address Space: This portion of the address space is used to access the PCIE controller’s downstream device configuration header information via configuration requests. Depending on the Bus number of the downstream device, it is up to the PCIE controller to decide whether to send a TYPE0 type or TYPE1 type configuration access.
The addresses of the above two address spaces are calculated from the configuration address space base address, BUS number, device number, function number, and register offset address, and can be accessed by word.
PCIE controller internal register space: This part of the address space is used to access the internal registers of the PCIE controller.
These registers are used to control the behavior and characteristics of the PCIE controller and belong to two address spaces with the PCIE configuration header space.
This address space is of type MEM, 64-bit address space, 4KB in size, with a base address equal to the value of 64-bit BAR0, which is assigned by the PCI scan software during initialization.
MEM address space: This part of the address space contains all the MEM address space of the devices downstream of the PCIE controller.
For the 32-bit address space, this is determined by the memory base and memory limit of the PCIE configuration header.
For the 64-bit address space, this is determined by the prefetchable memory base (combined upper 32 bits) and prefetchable memory limit (combined upper 32 bits) of the PCIE configuration header.
This address space is enabled and controlled by the command register bit1 of the PCIE configuration header.
I/O address space: This part of the address space contains all the I/O address space of the devices downstream of the PCIE controller.
It is determined by the IO base (combined upper 16 bits) and IO limit (combined upper 16 bits) of the PCIE configuration header.
This address space is enabled and controlled by the command register bit0 of the PCIE configuration header.
For the MEM address space and I/O address space, if there is no device connected downstream of an X1 port in X1 operation mode, the MEM and I/O address space can be disabled by setting bit0 and bit1 of the command register to 0.
PCIE Controller Enable
General configuration register 0 of the bridge configuration register contains the enable bits for the PCIE controller. It needs to be enabled when using the corresponding PCIE controller in order to access all address spaces of that controller and downstream devices, including configuration access to the controller.
22.3. Special Notes
PCIE Capability
The maximum MPS (Max Payload Size) and MRRS (Max Read Request Size) supported by the integrated PCIE controller of the bridge are both 256 bytes. The MPS setting can be set under the BIOS through the PCI negotiation mechanism. Since there is no negotiation mechanism for MRRS, BIOS developers need to set the MRRS value of the device to a value no larger than 256 bytes.
PCIE MSI
On 3A+7A systems, the destination address for PCI MSI interrupts is 0xfdf8000000 or 0x2ff00000.
The bridge converts the MSI message packets sent by the device to these two address segments into HT interrupt message packets and sends them to the processor.
PCIE Controller Performance
The PCIE controllers integrated in the bridge are x8, x4, and x1.
The P0 control port of PCIE_G0/G1/H is the x8 controller, the P0 port of PCIE_F0/F1 and the P1 port of PCIE_G0/G1/H are the x4 controllers, and the P1/P2/P3 port of PCIE_F0 and the P1 port of PCIE_F1 are the x1 controllers.
These three controllers have different numbers of internal flow-controlled buffers, with x8, x4, and x1 controllers decreasing in order, so for some high-bandwidth PCIE devices, using a controller with a larger number of flow-controlled buffers for the same data width will result in a performance improvement. Therefore, it is recommended to give preference to controllers with larger number of flow control buffers.
23. SPI Controller (D22:F0)
23.1. SPI Configuration Register (D22:F0)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Control Base Address Register |
|
R/W, RO |
18h-1Fh |
|
Memory Base Address Register |
|
R/W, RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (SPI - D22:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the SPI control registers and SPI memory space is enabled.
|
|
|
RO |
Reserved. |
The SPI controller consists of two address spaces: the control register space and the memory space.
CNL_BAR - Control Base Address Register
This register is used to configure the base address of the control registers of the SPI controler.
Address Offset: 10-13h
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the low address of the base address allocated to the SPI controller. |
|
|
RO |
The address space size of SPI controller is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 14-17h
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the SPI controller. |
MBAR - MEM Space Base Address Register
This register is used to configure the MEM space base address of the SPI controller.
Address Offset: 18-1Bh
Attribute: R/W, RO
Default value: 00000004h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the |
|
|
RO |
The SPI MEM space size is |
|
|
RO |
Set to |
|
|
RO |
Set to |
|
|
RO |
Set to |
Address Offset: 1C-1Fh
Attribute: R/W
Default value: 00000000h
Size: 32 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RW |
The software writes to this register field the high 32-bit address of the base address allocated to the SPI MEM space. |
23.2. SPI Control Register
| Address Offset | Name | Description |
|---|---|---|
|
|
Control register |
|
|
Status register |
|
|
Data register |
|
|
External register |
|
|
Parameter control register |
|
|
Chip select control register |
|
|
Timing control register |
Control Register (SPCR)
Offset address: 0x0
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
Interrupt output enable signal (active high) |
|
|
R/W |
|
System operation enable signal (active high) |
|
|
RO |
|
Reserved |
|
|
RO |
|
master mode select bit.
This bit is always held |
|
|
R/W |
|
Clock polarity bits |
|
|
R/W |
|
Clock phase.
|
|
|
R/W |
|
|
Status Register (SPSR)
Offset address: 0x1
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
Interrupt flag.
|
|
|
R/W |
|
Write register overflow flag bit.
|
|
|
RO |
|
Reserved |
|
|
RO |
|
Write register full.
|
|
|
RO |
|
Write register empty.
|
|
|
RO |
|
Read register full.
|
|
|
RO |
|
Read register empty.
|
Data Register (TxFIFO/RxFIFO)
Offset address: 0x2
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
W RO |
- |
Data transporting port. Data receiving port |
External Register (SPER)
Offset address: 0x3
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
Bytes transferred before sending an interrupt.
|
|
- |
- |
- |
Reserved |
|
|
R/W |
|
SPI interface mode control
|
|
|
R/W |
|
Set the ratio of the frequency division together with |
spre spr |
|
|
|
|
|
|
|
|
|
|
|
|
Frequency Division Factor |
|
|
|
|
|
|
|
|
|
|
|
|
Parameter Control Register (SFC_PARAM)
Offset address: 0x4
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
Clock division number selection. The frequency division factor is the same as the combination of |
|
|
R/W |
|
Dual I/O mode with higher priority than fast read |
|
|
R/W |
|
Fast Read Mode |
|
|
R/W |
|
SPI flash supports sequential address read mode |
|
|
R/W |
|
SPI flash read enable.
When disabled, |
Chip Select Control Register (SFC_SOFTCS)
Offset address: 0x5
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
|
R/W |
|
csn pin output value |
|
|
R/W |
|
When the bit is |
Timing Control Register (SFC_TIMING)
Offset address: 0x6
| Bit Field | Name | Read/Write | Initial Value | Description |
|---|---|---|---|---|
|
- |
- |
- |
Reserved |
|
|
R/W |
|
SPI flash read sampling mode
|
|
|
R/W |
|
The minimum invalidation time of the SPI Flash’s chip select signal, in terms of the clock period after frequency division. Calculation of
|
23.3. SPI Software Programming Guide
Read and Write Operations of the SPI Host Controller
Module Initialization
-
Stop SPI controller operation, write
0to thespebit of control registerspcr. -
Reset the status register
spsrand write1100_0000bto the register. -
Set the external register
sper, including the interrupt request conditionsper[7:6]and the dividing factorsper[1:0], refer to the register description for details. -
Configure SPI timing, including
cpol,cphaofspcrand mode ofsper.modeis1for standard SPI implementation and0for compatible mode. -
Configure interrupt enable,
spiebit ofspcr. -
Start the SPI controller and write
1to thespebit of the control registerspcr.
Send/transport Operations of the Module
-
Write data to the data transport register.
-
Since transporting and receiving occur simultaneously, the SPI slave device must perform a readout operation even if no valid data is sent.
Interrupt Handling
-
Receive the interrupt request.
-
Read the value of status register
spsr, ifspsr[2]is1, it means data transport is completed, ifspsr[0]is1, it means data has been received. -
Read or write the data transport register.
-
Write
1to the spif bit of status register spsr to clear the controller’s interrupt request.
Hardware SPI Flash Read
Initialization
-
Write
1to thememory_enbit ofSFC_PARAM. -
Set the read parameters (clock division, sequential address read, fast read, dual I/O, tCSH, etc.). These parameters are reset to the most conservative values.
Changing Parameters
If the SPI Flash used supports higher frequencies or offers enhanced features, modifying the corresponding parameters can greatly speed up the Flash access speed.
The parameter modification does not require turning off the SPI Flash read enable (memory_en).
Refer to the description of registers for details.
24. LPC Controller (D23:F0)
The LPC controller has the following features.
-
Compliant with LPC1.1 specification
-
Supports LPC access timeout counter
-
Supports Memory Read/Write access type
-
Supports Firmware Memory Read/Write access type (single byte)
-
Support I/O read/write access type
-
Support TPM I/O read/write access type
-
Support Memory access type address conversion
-
Support Serial IRQ specification, support 17 interrupt sources
24.1. LPC Configuration Register (D23:F0)
| Address Offset | Abbreviation | Description | Default value | Read/Write |
|---|---|---|---|---|
00h-01h |
|
Vendor ID |
|
RO |
02h-03h |
|
Device ID |
|
RO |
04h-05h |
|
PCI Command |
|
R/W, RO |
08h |
|
Revision ID |
|
RO |
09h |
|
Programming Interface |
|
RO |
0Ah |
|
Sub Class Code |
|
RO |
0Bh |
|
Base Class Code |
|
RO |
0Ch |
|
Cache Line Size |
|
RO |
0Eh |
|
Header Type |
|
RO |
10h-17h |
|
Fixed Control Register |
|
RO |
18h-1Fh |
|
Fixed Memory Register |
|
RO |
20h-27h |
|
Fixed I/O Register |
|
RO |
2Ch-2Dh |
|
Subsystem Vendor ID |
|
RO |
2Eh-2Fh |
|
Subsystem Identification |
|
RO |
3Ch |
|
Interrupt Line |
|
R/W |
3Dh |
|
Interrupt Pin |
|
RO |
Note: Address space not listed in the table indicates reserved.
* See the subsequent FIXCREG/FIXMREG/FIXIOREG and Appendix 2 for more information.
Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.
PCICMD - PCI Command Register (LPC - D23:F0)
Address Offset: 04-05h
Attribute: R/W, RO
Default value: 0000h
Size: 16 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
|
|
R/W |
This bit is used to control whether access to the LPC control registers and MEM space is enabled.
|
|
|
R/W |
This bit is used to control whether access to the LPC I/O space is enabled.
The address of the LPC I/O space is fixed starting from address
|
FIXCREG - Fixed Control Register
This register is not used as the BAR of the LPC configuration header.
Address Offset: 10-17h
Attribute: RO
Default value: 0000000010002004h
Size: 64 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
FIXMREG - Fixed MEM Register
This register is not used as the BAR of the LPC configuration header.
Address Offset: 18-1Fh
Attribute: RO
Default value: 0000000012000004h
Size: 64 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
FIXIOREG - Fixed I/O Register
This register is not used as the BAR of the LPC configuration header.
Address Offset: 20-27h
Attribute: RO
Default value: 000000FDFC000001h
Size: 64 bits
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
Reserved. |
The addresses of FIXCREG, FIXMREG, and FIXIOREG are the same as the BAR registers of the PCI configuration header, but these registers are not used as the BAR registers of the LPC configuration header.
Software can work around this hardware bug by modifying the PCI configuration read function so that the upper layer software is not affected. See Notes on the Use of the Software for more details.
24.2. LPC Access Address
The LPC controller consists of three address spaces: the control register space, the MEM space, and the I/O space.
The LPC control register space is used to configure the LPC controller, which is located in the fixed device address space of the bridge chip, starting at 0x1000,2000, with a size of 4KB.
The LPC MEM space is used to access the Memory/Firmware Memory devices mounted on the LPC bus.
The LPC MEM space is located in the fixed device address space of the bridge chip starting at 0x1200,0000 and is 32MB in size.
Processor accesses to the LPC MEM space are converted to LPC protocol Memory accesses and sent to the LPC bus.
Which type of Memory access is issued by the LPC controller is determined by the LPC controller’s control registers.
Addresses sent by the processor to this address space can be address converted.
The converted address is set by the LPC controller’s configuration register (LPC_MEM_TRANS).
24.3. LPC Interrupt
The LPC controller internally includes two types of interrupts: SIRQ interrupts and access timeout interrupts.
The LPC controller supports a total of 17 SIRQ interrupts, corresponding to the bits[16:0] of the interrupt-related register.
The access timeout interrupt corresponds to the bit[17] of the interrupt-related register.
The SIRQ interrupt is a level-triggered interrupt, and the value of the trigger level can be configured by the register. The software should configure the trigger level of the SIRQ interrupt before enabling the SIRQ interrupt of the LPC controller. The SIRQ interrupt does not need to be cleared by software.
The access timeout interrupt is edge-triggered, so if an LPC access timeout interrupt occurs, the software needs to write bit[17] of the interrupt clear register to clear the interrupt.
24.4. LPC Control Register
Control Register 0
Address Offset: 00-03h
Attribute: R/W
Default value: 0000FFFFh
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
SIRQ interrupt enable control. |
|
|
R/W |
LPC Memory space address translation enable. |
|
|
R/W |
The high 7-bit address ( |
|
|
R/W |
Threshold for LPC access timeout (minimum value 64). |
Control Register 1
Address Offset: 04-07h
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
LPC Memory space Firmware Memory access type configuration. |
|
|
R/W |
LPC interrupt enable, each bit corresponds to an interrupt source. For each interrupt source:
|
LPC Interrupt Status Register
Address Offset: 08-0Bh
Attribute: R/W
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
RO |
LPC Interrupt source indication, each bit corresponds to an interrupt source. For each interrupt source:
|
LPC Interrupt Clear Register
Address Offset: 0C-0Fh
Attribute: WO
Default value: 00000000h
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
WO |
LPC access timeout interrupt clear (write |
LPC SIRQ Interrupt Polarity Register
Address Offset: 10-13h
Attribute: R/W
Default value: 0000FFFBh
Size: 4
| Bit Field | Name | Read/Write | Description |
|---|---|---|---|
|
|
R/W |
LPC SIRQ interrupt polarity register, each bit corresponds to an interrupt source. For each interrupt source:
|
Appendix A: Table of Pin Multiplexing
The chip pins are multiplexed as shown in the following table.
Function 0 (Default) |
Function 1 |
Function 2 |
Function 3 |
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Note: All signals of HDA and LPC can only be multiplexed as a whole, and each pin cannot be controlled individually.
For example, if the AC97 function is enabled, pin HDA_SDI1/2 cannot be used as other functions.
Appendix B: Notes on the Use of the Software
Currently, there are five[2] problems that need to be fixed by the software for the bridge piece.
-
PCI device scanning problem
The correct value of the subclass code of the PCI device header of the PCIE bridge integrated in the bridge chip should be
0x04(for PCI type bridge), but this bridge chip will now be0x00(for Host type bridge).Solution: When the read configuration header access is found, if the access address is bus 0 of the device 9 to 20 and the address is
0x8, directly return0x06040001, and not return the hardware read value. -
PCI device scanning problem
For the PCIE bridge integrated in the bridge chip, when scanning the lower bus, when scanning the non-0 device, it should return an invalid value, but this bridge chip will return the configuration header of the 0 device, causing the 0 device to be found repeatedly.
Solution: For PCIE bridges integrated in the bridge, the lower bus only scans for device 0 and no other device number is scanned.
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PCI device scanning problem
The
Memory Space Enablecontrol bits of the PCI configuration headers of the OHCI (Function 0) and EHCI (Function 1) controllers of the USB devices (Device 4 and Device 5) are reversed. That is, theMemory Space Enablebit of EHCI controls the Mem space enable of OHCI, while theMemory Space Enablebit of OHCI controls the Mem space enable of EHCI.Solution: Fix by software.
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GMAC DMA64 problem
In 64-bit DMA mode, the high 32-bit register (
0x1094) of the GMAC’s transmit descriptor base address can only be read, but not written.Solution: Write to the high 32-bit register (
0x1094) by writing the following addresses{0x10a8[31:8], 0x1068[7:0]}. -
LPC
FIXIOREGproblemThe FIXCREG/FIXMREG/FIXIOREG of the LPC is used as an internal reserved register and is not used as a BAR in the PCI configuration header, but the hardware implementation incorrectly places its address in the location of the PCI configuration header BAR. The software should treat the
BARregister location of the LPC as an invalid BAR, but needs to enable I/O and MEM space access for the LPC.Solution: In the PCI configuration read access function, when the device found to be read is LPC (
B0:D23:F0) and the address is equal to the address ofBAR0/1/2/3/4/5(0x10to0x27), return data0directly. -
Concurrent access of DC control registers problem
The DC’s control registers do not support simultaneous write accesses by multiple processors, regardless of whether the destination registers for these write accesses are the same. That is, only one processor can write to the DC’s control register space at any given time.
Solution: The kernel prevents multiple processors from writing to the DC control register space at the same time by adding a lock.
