LoongArch Reference Manual - Volume 1: Basic Architecture

There are 32 General purpose Registers (GR), denoted as r0-r31, and the value of register r0 is always 0. The length of GR is recorded as GRLEN. The length of GR in LA32 is 32 bits, and the length of GR in LA64 is 64 bits. There is an orthogonal relationship between basic integer instructions and general registers. That is, from an architectural point of view, any register operand in this instruction can use any of the 32 GRs. The only exception is that the destination register implicit in the BL instruction must be r1. In the standard LoongArch Application Binary Interface (ABI), r1 is as storing the return address of a function call.

There is only one PC, which records the address of the current instruction. The PC register cannot be modified directly by instructions, it can only be modified indirectly by branch instructions, exception trap and exception return instructions. However, the PC register can be directly read as the source operand of some non-branch instructions. The length of PC is always the same as the length of GR.

Generally speaking, privileged resources cannot be directly accessed by application running at a non-privileged level, but when RPCNTL1/RPCNTL2/RPCNTL3 in CSR.MISC is set, the CSRRD instruction can be executed at the privilege level of PLV1/PLV2/PLV3 to read performance monitor counters. For more information about performance monitor counters, see Control and Status Registers Related to Performance Monitoring.

Some non-privileged functions that are enabled by default after power-on reset can be disabled by the system software during execution. By setting the DRDTL1/DRDTL2/DRDTL3 bits in CSR.MISC to 1, the execution of RDTIME instructions at the PLV1/PLV2/PLV3 level can be prohibited, or will trigger the Instruction Privilege error Exception (IPE).

The Cache coherency between the instruction Cache of a certain processor core and the Cache in other processor cores or Cache Coherenr I/O Master must be maintained by hardware.

The Cache coherency maintenance between the instruction Cache and the data Cache within the processor core can be implemented as hardware maintenance. This means that for the self-modifying code, the software does not need to use the CACOP instruction to maintain the Cache coherency between the instruction Cache and the data Cache within the same core. However, due to the pipeline structure and speculative instruction fetching behavior, the software still needs to use the IBAR instruction to ensure that the instruction fetching must be able to see the execution effect of the store instruction.

Instruction formats:

The ADD.W instruction performs the operation that the [31:0] bit data in the general register rj plus the [31:0] bit data in the general register rk; the resultant [31:0] bit is sign extension, then written into the general register rd.

The SUB.W instruction performs the operation that the [31:0] bit data in the general register rk minus the [31:0] bit data in the general register rj; the resultant [31:0] bit is sign extension, then written into the general register rd.

The ADD.D instruction performs the operation that the [63:0] bit data in the general register rj plus the [63:0] bit data in the general register rk; the result is written into the general register rd.

The SUB.D instruction performs the operation that the [63:0] bit data in the general register rj minus the [63:0] bit data in the general register rk; writes the result into the general register rd.

When the above instructions are executed, no special handling will be done on overflow.

Instruction formats:

The ADDI.W instruction performs the operation that the [31:0] bit data in the general register rj plus the 12-bit immediate si12 sign extension 32-bit data; the resultant [31:0] bit is sign extension, then written into the general register rd.

The ADDI.D instruction performs the operation that the [63:0] bit data in the general register plus to the 64-bit data after 12-bit immediate si12 sign-extension; the result is written into the general register rd.

ADDU16I.D shifts the 16-bit immediate sil6 logic to the left by 16 bits and then sign extensions the resultant data, the result plus [63:0] bit data in the general register rj, and the result of the addition is written into the general register rd. The ADDU16I.D instruction is used in conjunction with the LDPTR.W/D and STPTR.W/D instructions to accelerate GOT table-based access in position-independent codes.

When the above instructions are executed, no special handling will be done on overflow.

Instruction formats:

The ALSL.W instruction performs the operation that logical shift the [31:0] bit data in the general register rj to the left (sa2 + 1) and it plus the [31:0] bit data in the general register rk; then write the result into the general register rd after the sign extension.

ALSL.WU logical shift the [31:0] bit data in the general register rj to the left (sa2 + 1) bit and it plus the [31:0] bit data in the general register rk; then the result is [31:0] bit zero after expansion, write to general register rd.

The ALSL.D instruction performs the operation that logical shift the [63:0] bit data in the general register rj (sa2 + 1) to the left and it plus the [63:0] bit data in the general register rk; then the result is written into the general register rd.

When the above instructions are executed, no special handling will be done on overflow.

Instruction formats:

The LU12I.W instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate si20, then writes it into the general register rd after sign extension.

The LU32I.D instruction performs the operation that splice the bit data [31:0] in the general register rd behind the lowest bit of the 20-bit immediate si20 sign extension data; then the result is written into the general register rd.

The LU52I.D instruction performs the operation that splice the [51:0] bit data in the general register rj behind the lowest bit of the 12-bit immediate sil2 sign extension data; then the result is written into the general register rd.

When the above instructions are executed, no special handling will be done on overflow.

Instruction formats:

The SLT instruction performs the operation that compares the data in the general register rj with the data in the general register rk as signed integers. If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

The SLTU instruction performs the operation that compares the data in the general register rj with the data in the general register rk as unsigned integers. If the former is less than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

The data length compared by SLT and SLTU is consistent with the length of the general register of the executing machine.

Instruction formats:

The SLTI instruction performs the operation that compares the data in the general register rj and the 12-bit immediate sil2 sign extension data as a signed integer for size comparison. If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

The SLTUI instruction performs the operation that compares the data in the general register rj and the 12-bit immediate sil2 sign extension data as an unsigned integer for size comparison. If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

The data length compared by SLTI and SLTUI is consistent with the length of the general register of the executing machine. Note that for SLTUI instructions, immediate data is still sign extended.

Instruction formats:

The PCADDI instruction performs the operation that splice the 2 bit 0 behind the lowest bit of the 20-bit immediate data si20 and sign extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

The PCADDU12I instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate data si20 and signs extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

The PCADDU18I instruction performs the operation that splice the 18-bit 0 behind the lowest bit of the 20-bit immediate si20 and signs extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

The PCALAU12I instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate data si20 and sign extension; the resultant data plus the PC of the instruction; then the lowest 12 bits of the addition result are erased and written into the general register rd.

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

Instruction formats:

The AND instruction performs the bitwise AND operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

The OR instruction performs the bitwise OR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

The NOR instruction performs the bitwise OR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

The XOR instruction performs the bitwise XOR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

The ANDN instruction performs the operation that reverses the data in the general register rk bit by bit, then performs the bitwise AND operation with the data in the general register rk and the data in the general register rj; then the result is written into the general register rd.

The ORN instruction performs the operation that reverses the data in the general register rk bit by bit, then performs a bitwise OR operation with the data in the general register rk and the data in the general register rj, and the result is written into the general register rd.

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

Instruction formats:

The ANDI instruction performs the bitwise AND operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

The ORI instruction performs the bitwise OR operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

The XORI instruction performs the bitwise XOR operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

The NOP instruction is an alias for the instruction andi r0, r0, 0. Its function is only to occupy the 4-byte instruction code position and increase the PC by 4, except that it will not change any other software-visible processor state.

Instruction formats:

The MUL.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk, the result of the multiplication [31:0] bit data is signed and written into the general register rd.

The MULH.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as a signed number, the result of the multiplication [63:32] bit data is sign extension and written into the general register rd.

The MULH.WU instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as unsigned numbers, the result of the multiplication [63:32] bit data is sign extension and written into the general register rd.

The MUL.D instruction performs the operation that multiplies the [63:0] bit data in the general register rj with the [63:0] bit data in the general register rk, the result of the multiplication [63:0] bit data and written into the general register rd.

The MULH.D instruction performs the operation that multiplies the [63:0] bit data in the general register rj with the [63:0] bit data in the general register rk as a signed number, the result of the multiplication [127:64] bit data and written into the general register rd.

The MULH.DU instruction performs the operation that multiplies the [63:0] bit data in the general register rj and the [63:0] bit data in the general register rk as unsigned numbers, the result of the multiplication [127:64] bit data and written into the general register rd.

Instruction formats:

The MULW.D.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as a signed number, and the 64-bit product result is written into the general register rd.

The MULW.D.WU instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as unsigned numbers, and writes the 64-bit product result into the general register rd.

Instruction formats:

The DIV.W and DIV.WU instruction performs the operation that divide the [31:0] bit data in the general register rj by the [31:0] bit data in the general register rk, and the resulting quotient is sign extension and written into the general register rd.

The MOD.W and MOD.WU instruction performs the operation that divide the [31:0] bit data in the general register rj by the [31:0] bit data in the general register rk, and the resulting remainder is sign extension and written into the general register rd.

The DIV.D and DIV.DU instruction performs the operation that divide the [63:0] bit data in the general register rj by the [63:0] bit data in the general register rk, and the resulting quotient sign extension and written into the general register rd.

The MOD.D and MOD.DU instruction performs the operation that divide the [63:0] bit data in the general register rj by the [63:0] bit data in the general register rk, and the resulting remainder is sign extension and written into the general register rd.

When DIV.W, MOD.W, DIV.D and MOD.D perform division operations, the operands are all regarded as signed numbers. When DIV.WU, M0D.WU, DIV.DU and MOD.DU perform division operations, the source operands are all regarded as unsigned numbers.

Each pair of instructions for finding the quotient/remainder satisfies the result of DIV.W/MOD.W, DIV.WU/MOD.WU, DIV.D/MOD.D, DIV.DU/MOD.DU, the remainder and the dividend The sign is consistent and the absolute value of the remainder is less than the absolute value of the divisor.

When the divisor is 0, the result can be any value, but no exception will be triggered.

Instruction formats:

The SLL.W instruction performs the operation that logical left shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRL.W instruction performs the operation that logical right shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRA.W instruction performs the operation that arithmetical right shifts [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

The ROTR.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

The shift amount of the above-mentioned shift instruction is all [4:0] bit data in the general register rk, and is regarded as an unsigned number.

Instruction formats:

The SLLI.W instruction performs the operation that logical left shifts the [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRLI.W instruction performs the operation that logical right shifts the [31:0] bit data in the general register rj to the right, and writes the sign extension of the shift result into the general register rd.

The SRAI.W instruction performs the operation that arithmetical right shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The ROTRI.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general register rj, and the sign extension of the shift result is written into the general register rd.

The shift amounts of the above shift instructions are all 5-bit unsigned immediate ui5 in the instruction code.

Instruction formats:

The SLL.D instruction performs the operation that logical left shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRL.D instruction performs the operation that logical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRA.D instruction performs the operation that arithmetic right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The ROTR.D instruction performs the operation that cyclical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The shift amount of the above-mentioned shift instruction is all [5:0] bit data in the general register rk, and is regarded as an unsigned number.

Instruction formats:

The SLII.D instruction performs the operation that logicalleft shifts the bit data of [63:0] in the general register rj, and the sign extension of the shift result is written into the general register rd.

The SRLI.D instruction performs the operation that logical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The SRAI.D instruction performs the operation that arithmetically right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

The ROTRI.D instruction performs the operation that cyclical right shifts the [63:0] bit data in the general register rj, and the sign extension of the shift result is written into the general register rd.

The shift amount of the above-mentioned shift instruction is the 6-bit unsigned immediate ui6 in the instruction code.

Instruction formats:

The EXT.W.B instruction performs the operation that will sign extension the bit data of [7:0] in the general register rj and write it into the general register rd.

The EXT.W.H instruction performs the operation that will sign extension the bit data of [15:0] in the general register rj and write it into the general register rd.

Instruction formats:

The CLO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 1 is measured from bit 31 to bit 0, and the result is written into the universal register rd.

The CLZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 0 is measured from bit 31 to bit 0, and the result is written into the universal register rd.

The CTO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 1 is measured from bit 0 to bit 31, and the result is written into the universal register rd.

The CTZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 31, and the result is written into the universal register rd.

The CLO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 1 is measured from bit 63 to bit 0, and the result is written into the universal register rd.

The CLZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 1 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

The CTO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

The CTZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

Instruction formats:

The BYTEPICK.W instruction performs the operation that splice [31:0] bits in the general register rj behind [31:0] bits in the general register rk, and intercepts 4 consecutive bytes starting from the leftmost sa2 byte, and writes the 32-bit bit string symbol into universal register rd after expansion.

The BYTEPICK.D instruction performs the operation that splice [63:0] bits in the general register rj behind [63:0] bits in the general register rk, and intercepts 8 consecutive bytes starting from the leftmost sa3 byte, and writes the 64-bit bit string symbol into universal register rd after expansion.

Instruction formats:

The REVB.2H instruction performs the operation that arranges the 2 bytes in the [15:0] bits in the general register rj in reverse order to form the [15:0] bits of the intermediate result, and reverses the 2 bytes in the [31:16] in the general register rj Arrange the [31:16] bits of the intermediate result, and write the 32-bit intermediate result sign extended to the general register rd.

The REVB.4H instruction performs the operation that arranges the 2 bytes in the [15:0] bits of the general register rj in reverse order and writes them into the [15:0] bits of the general register rd, and writes 2 words in the [31:16] bits of the general register rj. Write the sections in reverse order to bits [31:16] of the general register rd, and write the 2 bytes of bits [47:32] in the general register rj in reverse order to bits [47:32] of the general register rd. The 2 bytes in the [63:48] bits in the register rj are written in the [63:48] bits in the general register rd in reverse order.

The REVB.2W instruction performs the operation that writes the 4 bytes in the [31:0] bits of the general register rj into the [31:0] bits of the general register rd in reverse order, and writes 4 of the [63:32] bits in the general register rj. Write the byte in reverse order to bits [63:32] of the general register rd.

REVB.D writes the 8 bytes in the [63:0] bits in the general register rj into the general register rd in reverse order.

Instruction formats:

The REVH.2W instruction performs the operation that writes two half-words in bit [31:0] of general purpose register rj into bit [31:0] of general purpose register rd, and two half-words in bit [63:32] of general purpose register rj into bit [63:32] of general purpose register rd.

The REVH.D instruction performs the operation that write four half-words in [63:0] bit of universal register rj in reverse order to universal register rd.

Instruction formats:

The BITREV.4B instruction performs the operation that the [7:0] bit in general register rj is arranged in reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general register rj is arranged in reverse order, and the [31:24] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

The BITREV.8B instruction performs the operation that the [7:0] bit in general register rj is arranged in reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general register rj is arranged in reverse order, the [31:24] bit in general register rj is arranged in reverse order; the [39:32] bit in general register rj is arranged in reverse order; the [47:40] bit in general register rj is arranged in reverse order; the [55:48] bit in general register rj is arranged in reverse order; the [63:56] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

Instruction formats:

The BITREV.W instruction performs the operation that the [31:0] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

The BITREV.D instruction performs the operation that the [63:0] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

Instruction formats:

The BSTRINS.W instruction performs the operation that replaces the [msbw:lsbw] bit in the lowest 32 bits of the general register rd with the [msbw-lsbw:0] bit in the general register rj, and the resulting 32-bit result is sign extension and written into the general register rd.

The BSTRINS.D instruction performs the operation that replaces the [msbd:lsbd] bit in the general register rd with the [msbd-lsbd:0] bit in the general register rj, and the rest of the general register rd remains unchanged.

Instruction formats:

BSTRPICK.W extracts the [msbw:Isbw] bit in the general register rj and zero-extends it to 32 bits, and the formed 32-bit intermediate result is sign extension and written into the general register rd.

BSTRPICK.D extracts the [msbd:Isbd] bit in the general register rj and zero-extends it to 64 bits and writes it into the general register rd.

Instruction formats:

MASKEQZ and MASKNEZ instructions perform conditional assignment operations. When MASKEQZ is executed, if the value of the general register rk is equal to 0, the general register rd is set to 0, otherwise it is assigned to the value of the rj register.

When MASKNEZ is executed, if the value of the general register rk is not equal to 0, the general register rd is set to 0, otherwise it is assigned to the value of the rj register.

Instruction formats:

The BEQ instruction performs the operation that compares the values of general register rj and general register rd, if the two are equal, jump to the target address, otherwise it does not jump.

The BNE instruction performs the operation that compares the values of general register rj and general register rd, if the two are not equal, jump to the target address, otherwise it does not jump.

The BLT instruction performs the operation that compares the values of general register rj and general register rd as signed numbers. If the former is smaller than the latter, it jumps to the target address, otherwise it does not jump.

The BGE instruction performs the operation that compares the values of general register rj and general register rd as signed numbers. If the former is greater than or equal to the latter, it jumps to the target address, otherwise it does not jump.

The BLTU instruction performs the operation that compares the values of general register rj and general register rd as unsigned numbers. If the former is less than the latter, it jumps to the target address, otherwise it does not jump.

The BGEU instruction performs the operation that compares the values of general register rj and general register rd as unsigned numbers. If the former is greater than or equal to the latter, it jumps to the target address, otherwise it does not jump.

The calculation method of the jump target address of the above-mentioned six branch instructions is to logically shift the 16-bit immediate offs16 in the instruction code by 2 bits and then sign expand, and the resulting offset value is added to the PC of the branch instruction.

Instruction formats:

The BEQZ instruction performs the operation that judges the value of the general register rj, if it is equal to 0, jump to the target address, otherwise it does not jump.

The BNEZ instruction performs the operation that judges the value of the general register rj, if it is not equal to 0, it jumps to the target address, otherwise it does not jump.

The jump target address of the above two branch instructions is to logical left shift the 21-bit immediate offs21 in the instruction code by 2 bits and then sign extension, and the resulting offset value is added to the PC of the branch instruction.

Instruction formats:

The B instruction performs the operation that jumps to the target address unconditionally. The jump target address is to logical left shift the 26-bit immediate offs26 in the instruction code by 2 bits and then sign extension, and the resulting offset value is added to the PC of the branch instruction.

Instruction formats:

The BL instruction performs the operation that jumps to the target address unconditionally, and writes the result of adding 4 to the PC value of the instruction into the No.1 general register r1.

The jump target address of the instruction is to shift the 26-bit immediate offs26 in the instruction code to the left by 2 bits and then sign extend it. The shift value is added to the PC of the branch instruction.

In LA ABI, the No.1 general register r1 serves as the return address register ra.

Instruction formats:

JIRL jumps to the target address unconditionally, and the PC value of the instruction plus 4; then writes the result into the general register rd.

The jump target address of the instruction is to logically shift the 16-bit immediate offs16 in the instruction code by 2 bits to the left and then sign extension, and the resulting offset value is added to the value in the general register rj.

When rd is equal to 0, the function of JIRL is a common non-call indirect jump instruction.

JIRL with rd equal to 0, rj equal to 1 and offs16 equal to 0 is often used as an indirect jump from call return.

Instruction formats:

LD.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign extension and writes it into the general register rd.

LD.{BU/HU/WU} retrieves one byte/halfword/word data from the memory and writes it into the general register rd after zero extension.

ST.{B/H/W/D} writes [7:0]/[15:0]/[31:0]/[63:0] bit data in general register rd into the memory.

The memory access address calculation method of the above instruction is sum the value in the general register rj and the sign extension 12-bit immediate value sil2.

For LD.{H[U]/W[U]/D} and ST.{B/H/W/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as their memory access addresses are naturally aligned When the memory access address is not naturally aligned, if the hardware implementation supports non-aligned memory access and the current computing environment is configured to allow non-aligned memory access, then the non-aligned exception will not be triggered, otherwise a non-aligned exception will be triggered.

Instruction formats:

LDX.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign extension and writes it into the general register rd.

LDX.{BU/HU/WU} retrieves one byte/halfword/word data from the internal zero extension and writes it into the general register rd.

STX.{B/H/W/D} writes [7:0], [15:0], [31:0] and [63:0] bits of data in the general register rd into the memory.

The memory access address calculation method of the above instruction is the value in the general register rj and the value in the general register rk. For LDX.{H[U]/W[U]/D} and STX.{B/H/W/D} instructions, no matter what kind of hardware implementation and environment configuration, as long as its memory access address is natural Aligned, will not trigger non-aligned exception; when the fetch address is not naturally aligned, if the hardware implementation supports non-aligned memory access and the current computing environment is configured to allow non-aligned memory access, then the non-aligned exception will not be triggered, otherwise a non-aligned exception will be triggered.

Instruction formats:

LDPTR.{W/D} retrieves the data of a word/double word from the internal sign extension and writes it into the general register rd.

STPTR.{W/D} Write the data of bits [31:0]/[63:0] in the general register rd into the memory.

The memory access address calculation method of the above instruction is to logical left shift the 14-bit immediate data si14 by 2 bits, sign extension, and then sum the value in the general register rj.

For LDPTR.{W/D} and STPTR.{W/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as the memory access address is naturally aligned, the non-aligned exception will not be triggered; when the memory address is not naturally aligned, if the hardware implementation supports unaligned memory access and the current computing environment is configured to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will trigger the unaligned exception.

LDPTR.{W/D}, STPTR.{W/D} instructions are used in conjunction with ADDU16I.D instructions to accelerate GOT table-based access in position-independent codes.

Instruction formats:

PRELD Reads a cache-line of data from memory in advance into the Cache. The access address is the 12bit immediate number of the value in the general register rj plus the symbol extension.

The processor learns from the hint in the PRELD instruction what type will be acquired and which level of Cache the data to be taken back fill in, hint has 32 optional values (0 to 31), 0 represents load to level 1 Cache, and 8 represents store to level 1 Cache. The remaining hint values are not defined and are processed for nop instructions when the processor executes.

If the Cache attribute of the access address of the PRELD instruction is not cached, then the instruction cannot generate a memory access action and is treated as a NOP instruction. The PRELD instruction will not trigger any exceptions related to MMU or address.

Instruction formats:

The PRELDX instruction continuously prefetches data from memory into the Cache according to the configuration parameters, and the continuously prefetched data is a block (block) of length block_size starting from the specified base address (base) with a number of (block_num) spacing stride. The base address is the sum of the [63:0] bits in the general register rj and the sign extension [15:0] bits in the general register rk. The [I16] bits in general register rk are the address sequence ascending and descending flag bits, with 0 indicating address ascending and 1 indicating address descending. The value of bits [25:20] in general register rk is block_size, the basic unit of block_size is 16 bytes, so the maximum length of a single block is 1KB. The value of bits [39:32] in general register rk is block_num-1, so a single instruction can prefetch up to 256 blocks. The value of bits [59:44] in the block general register rk is treated as a signed number and defines the stride between adjacent blocks, the basic unit of stride is 1 byte. The value of bits [39:32] in rk is block.num-1, so a single instruction can prefetch up to 256 blocks. The value of bits [59:44] in general register rk is regarded as a signed number, which defines the corresponding The basic unit of stride and stride between adjacent blocks is 1 byte.

hint in the PRELDX instruction indicates the type of prefetch and the level of Cache into which the fetched data is to be filled. hint has 32 selectable values from 0 to 31. Currently, hint=0 is defined as load prefetch to level 1 data Cache, hint=2 is defined as load prefetch to level 3 Cache, hint-8 is defined as store prefetch to level 1 data Cache. The meaning of the rest of hint values is not defined yet, and the processor executes it as NOP instruction.

If the Cache attribute of the access address of the PRELDX instruction is not cached, then the instruction cannot generate a memory access action and is treated as a NOP instruction.

The PRELDX instruction does not trigger any exceptions related to MMU or address.

Instruction formats:

LDGT/LDLE.B/H/W/D fetches a byte/half word word/double word data symbol extension from memory and writes it to the general register rd.

STGT/STLE.B/H/W/D writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data from the general register rd to memory.

The access addresses of the above instructions come directly from the values in the general register rj. The access addresses of the above instructions are required to be naturally aligned, otherwise a non-alignment exception will be triggered.

B/H/W/D and STGT.B/H/W/D instructions check whether the value in general register rj is greater than the value in general register rk, and terminate the access operation and trigger the bound check exception if the condition is not satisfied; B/H/W/D and STLE.B/H/W/D instructions check whether the value in general register rj is less than or equal to the value in general register rk, and if the condition is not satisfied, the access operation is terminated and the bound check exception is triggered.

Instruction formats:

The AM* atomic access instruction performs a sequence of “read-modify-write” operations on a memory cell atomically. Specifically, it retrieves the old value at the specified address in memory and writes it to the general register rd, performs some simple operations on the old value in memory and the value in the general register rk, and then writes the result of the operations back to the specified address in memory. The entire “read-modify-write” process is atomic, meaning that the processor executing the instruction does not perform any other access-write operations nor does it trigger any exceptions during the time between the return of the access read operation data and the global visibility of the access write operation, and no other processor cores or cache-consistent. The module has global visibility of the execution of the write operation on the Cache row where the instruction accesses the object.

The access address of an AM* atomic access instruction is the value of the general register rj. The access address of an AM* atomic access instruction always requires natural alignment, and failure to meet this condition will trigger a non-alignment exception.

Atomic access instructions ending in .W and .WU read and write memory and intermediate operations with a data length of 32 bits, while atomic access instructions ending in .D and .DU read and write memory and intermediate operations with a data length of 64 bits. Whether ending in .W or .WU, the data of a word retrieved from memory by an atomic access instruction is symbolically extended and written to the general register rd.

AMSWAP[.DB].{W/D} instruction writes the new value of memory from the general register rk. AMADD[.DB].{W/D} instruction writes the new value of memory from the result ofold value of memory plus the value in general register rk. AMAND[DB].{W/D} instruction writes the new value to memory as a result of the bitwise AND operation of the old value in memory and the value in general register rk. AMOR[DB].{W/D} instruction writes a new value to memory from AMXOR[.DB]. The new value written to memory by the {W/D} instruction is the result of the bitwise OR operation of the old value in memory and the value in general register rk. AMMAX[_DB].{W/D} instruction writes the new value to memory as the result of the bitwise AND operation of the old value in memory and the value in general register rk. The new value written to memory is the maximum value obtained by comparing the old value in memory with the value in general register rk as a signed number. [_DB].{W/D} instruction The new value written to memory is the minimum value obtained by comparing the old value of memory with the value in general register rk as if it were a signed number. The new value written to memory by the AMMAX[DB].[WU/DU] instruction is the maximum value obtained by comparing the old value in memory with the value in general register rk as an unsigned number. AMMIN[_DB].{WU/DU} instruction writes the new value to memory by comparing the old value in memory with the value in general register rk as an unsigned number. The new value written to memory is the minimum value obtained by comparing the old value in memory with the value in general register rk as an unsigned number.

AM*_DB.W[U]/D[U] instruction not only completes the above atomized operation sequence, but also implements the data barrier function at the same time. That is, all access operations preceding the atomic access instruction in the same processor core are completed before such atomic access instructions are allowed to be executed, and all access operations following the atomic access instruction in the same processor core are allowed to be executed only after such atomic access instructions are executed.

If the AM* atomic memory access instruction has the same register number as rd and rj, the execution will trigger an Instruction Non-defined Exception.

If the AM* atomic memory access instruction has the same register number as rd and rk, the execution result is uncertain. Please software to avoid this situation.

Instruction formats:

AM{SWAP/ADD}[_DB].{B/H} and AM{SWAP/ADD}[_DB].{W/D} are atomic access instructions, can atomically complete the "read - modify - write" sequence of operations on a memory cell, the main difference is that the data being accessed is byte/half-word or word/double-word.

AM{SWAP/ADD}[_DB].{B/H} retrieve the old byte/half word value at the specified address in memory and write it to the general register rd after symbol extension, At the same time, the old value in the memory is exchanged or added with the byte/half-word value of the general register rk [7:0]/[15:0] bit, and then the byte/half-word results will be written back to the specified address of the memory. The entire "read-modify-write" process is atomic, meaning that the execution of the instruction, from the access to read the data return to the access to write the implementation of the effect of global visibility at the time, the processor executing the instruction neither executes other memory access write operations nor triggers any exception, and no other processor core or Cache coherence module can globally see the execution effect of the write operation on the Cache line of the object accessed by the instruction.

AM{SWAP/ADD}[_DB].{B/H} The access address of an atomic access instruction is the value of general-purpose register rj.

AM{SWAP/ADD}[_DB].H access address of an atomic access instruction is always required to be naturally aligned, and a non-alignment exception is triggered if this condition is not met.

In addition to the above atomic sequence of operations, the AM{SWAP/ADD}_DB.{B/H} instruction also implements the data barrier function. That is, when this kind of atomic access instruction is allowed to execute before, all in the same processor core before the atomic access instruction access operations have been completed; at the same time, only until the completion of this kind of atomic access instruction execution, all in the same processor core after the atomic access instruction access operation is allowed to execute.

If rd and rj have the same register number in AM{SWAP/ADD}[_DB].{B/H} instruction, there is no exception for trigger instruction.

If the register numbers of rd and rk in an AM{SWAP/ADD}[_DB].{B/H} instruction are the same, the execution result is uncertain, so please ask the software to avoid this situation.

Instruction formats:

AMCAS[_DB].{B/H/W/D} instruction performs a byte/half-word/word/double-word sized Compare-and-Swap operation on a specified address in memory: The byte/half-word/word/double-word value retrieved from memory (old memory value) is compared with the value stored in the [7:0]/[15:0]/[31:0]/[63:0] location of the general-purpose register rd (expected value), and the value stored in the [7:0]/[15:0]/[31:0]/[63:0] location of the general-purpose register rk (new value) is written to the same location in the memory only when the comparison results are equal. Regardless of whether the comparison results are equal or not, the old memory value is written to the general-purpose register rd after sign expansion.

The above process, If a write occurs because the old memory value is equal to the expected value, then the entire "read - modify - write" process is atomic, that is, from the access to the read operation data return to the access to the write operation to perform the effect of the global visibility of this time, the processor executing the instruction is neither the implementation of the other access to the write operation nor trigger Any exception, and no other processor core or Cache Consistency Module to the instruction access object where the Cache line of the write operation of the execution of the effect of the global visible.

AMCAS[_DB].{H/W/D} The access address of the instruction is the value of general-purpose register rj, and the access address is always required to be naturally aligned, if this condition is not met, a non-aligned exception will be triggered.

In addition to the above atomic sequence of operations, the AMCAS_DB.{B/H/W/D} instruction also implements the data barrier function. That is, when this kind of atomic access instruction is allowed to execute before, all in the same processor core before the atomic access instruction access operations have been completed; at the same time, only when this kind of atomic access instruction execution is completed, all in the same processor core after the atomic access instruction access operations are allowed to execute.

Instruction formats:

The two pairs of instructions, LL.W and SC.W, LL.D and SC.D, are used to implement an atomic “read, modify, and write” sequence of memory access operations. The LL.{W/D} instruction retrieves a word/double-word data from the specified address of the memory and writes it to the general register rd after sign extension, and the paired SC. {W/D} instruction operates on the same length of data and has the same access Memory address. The atomic maintenance mechanism for the sequence of memory access operations is that when LL.{W/D} is executed, the access address is recorded and the previous flag is set (LLbit is set to 1), and the LLbit is checked when the SC.{W/D} instruction is executed. Only when the LLbit is 1, the write action will actually occur, otherwise it will not be written. When the software needs to successfully complete an atomic “read-modify-write” memory access operation sequence, it needs to construct a loop to repeatedly execute the LLSC instruction pair until the SC is successfully completed. In order to construct this loop, the SC.[W/D] instruction will write the flag of its execution success (or simply the LLbit value seen when the SC instruction is executed) into the general register rd and return.

During the execution of the paired LLSC, the following events will clear the LLbit to 0:

If the memory access attribute of the LLSC instruction to the access address is not Cached, then the execution result is uncertain.

Instruction formats:

The SC.Q instruction is similar to the SC.D instruction and is used in conjunction with the LL.D instruction to implement an atomic "read-modify-write" access sequence for 128-bit data.

SC.Q writes the 128-bit data {GR[rk][63:0], GR[rd][63:0]} obtained by splicing the general-purpose registers rk and rd into memory, and its access address is the value of the general-purpose register rj. SC.Q instruction will check LLbit when executing, and only when LLbit is 1, then it will write, otherwise it will not write, SC.Q instruction will write the flag of success or failure (also can be understood as the value of LLbit when SC.Q instruction executes) into general register rd and return to the memory.

The access address of SC.Q instruction is always required to be 16-byte aligned, if this condition is not met, a non-aligned exception will be triggered.

If the SC.Q instruction’s memory access attribute for the access address is not consistently cacheable (CC), the result of the execution is indeterminate.

Instruction formats:

LL.ACQ.{W/D} is an LL.{W/D} instruction with read-acquire semantics, that is, only when LL.ACQ.{W/D} is executed (globally visible), all subsequent access operations can start executing (globally visible effect); SC.REL.{W/D} is an SC.{W/D} instruction with write-release semantics, that is, only when SC.REL.{W/D} is executed (globally visible), all access operations can start executing (globally visible effect).

The LL.ACQ.{W/D} instruction fetches a word/double word of data symbol expansion from the specified address in memory and writes it to the general-purpose register rd, and at the same time records the access address and places a flag (LLbit set to 1). The SC.REL.{W/D} instruction conditionally writes the word/double-word value of [31:0]/[63:0] in the general-purpose register rd to the specified address in the memory, whether or not to write to the memory depends on the LLbit, and only when the LLbit is 1 does it really generate a write action, otherwise it does not write. SC.REL instruction will write the flag of success or failure of its execution (which can be simply understood as the LLbit value seen by the SC.REL instruction when it is executed) into the general-purpose register rd and return it, regardless of whether it writes to the memory or not.

During paired LL-SC execution, the following events clear the LLbit to zero:

LL.ACQ and SC.REL instructions always require a natural alignment of the access address, if this condition is not met a non-alignment exception is triggered.

If the LL.ACQ and SC.REL instructions direct that the store access attribute of the access address is not cache-consistent (CC), then the result of the execution is indeterminate.

Instruction formats:

The DBAR instruction is used to complete the barrier function between load/store memory access operations. The immediate hint it carries is used to indicate the synchronization object and synchronization degree of the barrier.

A hint value of 0 is mandatory by default, and it indicates a fully functional synchronization barrier. Only after all previous load/store access operations are completely executed, the DBAR 0 instruction can be executed; and only after the execution of DBAR 0 is completed, all subsequent load/store access operations can be executed.

If there is no special function implementation, all other hint values must be executed according to hint=0.

Instruction formats:

The IBAR instruction is used to complete the synchronization between the store operation and the instruction fetch operation within a single processor core. The immediate hint it carries is used to indicate the synchronization object and synchronization degree of the barrier.

A hint value of 0 is mandatory by default. It can ensure that the instruction fetch after the IBAR 0 instruction must be able to observe the execution effect of all store operations before the IBAR 0 instruction.

Instruction formats:

CRC[C]W.{B/H/W/D}.W is used to calculate the CRC-32 checksum, which stores the 32-bit cumulative CRC checksum stored in the general register rk in the general register rj [7:0]/[15:0]/[31:0]/[63:0] bit message, get a new 32-bit CRC checksum according to the CRC-32 checksum generation algorithm, and write it after sign extension into the general register rd. The difference is that CRC.W.{B/H/W/D}.W uses IEEE802.3 polynomial (polynomial value is 0xEDB88320), CRCC.W.{B/H/W/D}.W uses Castagnoli polynomial (polynomial value is 0x82F63B78). The CRC instructions defined in this manual only support the “LSB first” (little endian) standard, which means that the lowest bit of data (little endian) is transmitted first, and the lowest bit of the data is mapped to the coefficient of the most significant term of the message polynomial.

Instruction formats:

Executing the SYSCALL instruction will immediately and unconditionally trigger the system call exception.

The information carried in the code field in the instruction code can be used as a parameter passed by the exception handling routine.

Instruction formats:

Executing the BREAK instruction will immediately and unconditionally trigger the breakpoint exception.

The information carried in the code field in the instruction code can be used as a parameter passed by the exception handling routine.

Instruction formats:

The value in general register rj and general register rk are compared as signed numbers. If the comparison conditions are not met, an exception for address bound checking is triggered. For the ASRTLE.D instruction, if the value in the general register rj is greater than the value in the general register rk, an exception is triggered; for the ASRTGT.D instruction, if the value in the general register rj is less than or equal to the value in the general register rk, an exception is triggered.

Instruction formats:

The LoongArch instruction system defines-a constant frequency timer, whose main body is-a 64-bit counter called StableCounter. StableCounter is set to 0 after reset, and then increments by 1 every counting clock cycle. When the count reaches all 1s, it automatically wraps around to 0 and continues to increment. At the same time, each timer has a software-configurable globally unique-number, called Counter ID. The characteristic of the constant frequency timer is that its timing frequency remains unchanged after reset, no matter how the clock frequency of the processor core changes.

The RDTIME{L/W}.W and RDTIME.D instructions are used to read constant frequency timer information, the StableCounter value is written into the general register rd, and the Counter ID number information is written into the general register rj. The difference between the three instructions is the difference in the Stable Counter information read. RDTIMEL.W reads the [31:0] bits of the Counter, RDTIMEH.W reads the [63:32] bits of the Counter, and RDTIME.D reads The entire 64-bit Counter value. On a 64-bit processor, the 32-bit value read by the RDTIME{L/H}.W instruction is sign extension and written to the general register rd. The RDTIME(L/H).W instruction is defined so that the 64-bit Counter can also be accessed on a 32-bit processor.

Instruction formats:

The CPUCFG instruction is used to dynamically identify which features of LoongArch are implemented in the running processor during the execution of the software. The realization of the functional characteristics of these instruction systems is recorded in the series of configuration information words. One configuration information word can be read once the CPUCFG instruction is executed.

When using the CPUCFG instruction, the source operand register rj stores the number of the configuration information word to be accessed, and the configuration information word information read after the instruction is executed is written into the general register rd. In LA64, each configuration information word is 32 bits, which is written into the result register after the sign extension.

The configuration information word contains-series of configuration bits (fields), and its record form is CPUCFG.<configuration word number>.<configuration information mnemonic name>[bit subscript], where the single bit configuration bit is marked as bitXX, which means The XX bit of the configuration word; the bit under the multi-bit configuration field is marked as bitXX:YY, which means the continuous (XX-YY+1) bit from the XX bit to the YY bit of the configuration word. For example, the 0th bit in the configuration word No.1 is used to indicate whether to implement LA32. Record this configuration information as CPUCFG.1.LA32[bit0], where 0x1 indicates that the font size of the configuration information word is No.1, and LA32 indicates this configuration The mnemonic name of the information field is called LA32, and bit 0 means that the field of LA32 is located at bit 0 of the configuration word. The PALEN field of the number of physical address bits supported by the 11th to 4th digits of the configuration word No.1 is recorded as CPUCFG.1.PALEN[itl1:4].

The configuration information accessible by the CPUCFG instruction in the Godson architecture is listed in the table. CPUCFG access to undefined configuration words will read back all 0 values. The undefined field in the defined configuration word can be read back to any value when CPUCFG is executed, and the software should not make any interpretation of it.

Single-precision floating-point numbers have a length of 32 bits and are organized into the following format:

According to the different values of the fields of S, Exponent and Fraction, the floating-point number values represented are shown in the table:

For the specific meaning of ±∞, SNaN and QNaN, please refer to the IEEE 754-2008 standard specification.

According to the different values of the fields of S, Exponent and Fraction, the floating-point number values represented are shown in the table:

For the specific meaning of ±∞, SNaN and QNaN, please refer to the IEEE 754-2008 standard specification.

The non-numerical results produced by floating-point number instructions either come from NaN propagation or are directly generated. There are two situations where NaN propagation is required.

Case 1: When the instruction generates an Invalid Operation floating-point exception due to a source operand containing SNaN, but the InvalidOperation floating-point exception enable is invalid, a QNaN result will be generated at this time. The value of this QNaN is to select the SNaN with the highest priority in the source operand and propagate it to the corresponding NaN.

The rule for determining the priority of the source operand is: if there are two source operands fj and fk, then the priority of fj is higher than fk; if there are three source operands fa, fj and fk, then the priority of fa is higher than fj, fj have higher priority than fk.

The value generation rules for propagation of SNaN to QNaN are as follows:

Case 2: When there is no SNaN in the source operand but QNaN exists, the QNaN with the highest priority is selected as the result of this instruction. At this time, the way of judging the priority of the source operand is the same as in the above situation.

Except for the above two cases, other cases that need to produce QNaN results will be directly set to the default QNaN value. The default single-precision QNaN value is 0x7FC00000, and the default double-precision QNaN value is 0x7FF8000000000000.

There are 32 FRs, denoted as f0-f31, each of which can be read and written. Only when only floating-point instructions that manipulate single-precision floating-point numbers and word integers are implemented, the length of FR is 32 bits. Under normal circumstances, the length of FR is 64 bits, regardless of the LA32 or LA64. There is an “orthogonal” relationship between basic floating-point instructions and floating-point registers, that is, from an architectural perspective, any floating-point register operand in these instructions can use any one of the 32 FRs.

When the floating-point register records a single-precision floating-point number or word integer, the data always appears in the [31:0] bits of the floating-point register, at this time the [63:32] bits of the floating-point register can be any value.

There are 8 CFRs, denoted as fcc0-fcc7, each of which can be read and written. The length of CFR is 1 bit. The result of the floating-point comparison will be written into the condition flag register. When the comparison result is true, it is set to 1, otherwise it is set to 0. The judgment condition of the floating-point branch instruction comes from the condition register.

There are 4 FCSRs, denoted as fcsr0-fcsr3. Among them, fcsr1-fcsr3 are aliases of some fields in fcsr0, that is, accessing fcsrl-fcsr3 is actually accessing some fields of fcsr0. When the software writes fcsr1-fcsr3, the corresponding field in fcsr0 is modified while the remaining bits remain unchanged. The definition of each field of fcsr0 is shown in the table.

FCSR1 is the alias of the Enables field in FCSR0. Its location is the same as in FCSR0.

FCSR2 is the alias of the Cause and Flags fields in FCSR0. The location of each field is consistent with FCSR0.

FCSR3 is the alias of the RM field in FCSR0. Its location is the same as in FCSR0.

An invalid operation exception notification signal will be sent if and only if there is no valid defined result. If no exception is triggered, a QNaN will be generated. Please refer to Characteristics of Accessing Control and Status Registers of the IEEE 754-2008 specification for specific determination details of extraordinary operation exceptions.

If an exception is allowed to fall into: the result register is not modified, the source register remains.

If exceptions are prohibited from trapping: If no other exceptions occur, QNaN is written to the target register.

In the division operation, when the divisor is 0 and the dividend is-a limited non-zero data, the division by zero exception is signaled.

If an exception is allowed to fall into: the result register is not modified, the source register remains

If an exception is forbidden to fall into: if no trap occurs, the result is a signed infinite value.

Regarding the exponent field as an unbounded rounding of the intermediate result, when the absolute value of the result obtained exceeds the maximum finite number of the target format, an overflow exception will be notified.(This exception sets both inexact exception and flag bit)

If an exception is allowed to fall into: the result register is not modified, the source register remains.

If exceptions are forbidden to fall into: If no trap occurs, the final result is determined by the rounding mode and the sign of the intermediate result.

When the detection result is a small non-zero value, an underflow exception will occur. The way to detect small non-zero values is to detect after rounding. that is, for a non-zero result is in (-2Emin, 2Emin), the result is considered to be a small non-zero value (Single-precision number Emin=-126, double-precision number Emin=-1022). When FCSR.Enable.U=0, if the result is detected, a non-zero tiny value:

When FCSR.Enable.U=1, if the result is a non-zero tiny value, regardless of whether the final rounded result of the floating-point operation is accurate or inaccurate, it will trigger a floating-point exception trap.

FPU generates inaccurate exceptions when the following situations occur:

If an exception is allowed to fall: If an inexact exception trap is enabled, the result register is not modified and the source register is retained. Because this execution mode affects performance, inaccurate exception traps are only enabled when necessary.

If an exception is prohibited, trapping is prohibited: If no other software trap occurs, the rounding or overflow result is sent to the destination register.

Instruction formats:

The FADD.{S/D} instruction performs the operation that the single-precision/double-precision floating-point number in the floating-point register fj plus the single-precision/double-precision floating-point number in the floating-point register fk; then writes the result of the single-precision/double-precision floating-point number to floating-point register fd. Floating-point addition operation follows the specification of addition(x,y) operation in the IEEE 754-2008 standard.

The FSUB.{S/D} instruction performs the operation that the single-precision/double-precision floating-point number in the floating-point register fj minus the single-precision/double-precision floating-point number in the floating-point register fk, and write the result of the single-precision/double-precision floating-point number to floating-point register fd. The floating-point subtraction operation follows the subtraction(xy) operation specification in the IEEE 754-2008 standard.

The FMUL.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj by the single-precision/double-precision floating-point number in the floating-point register fk, and writes the result of the single-precision/double-precision floating-point number To the floating-point register fd. The floating-point multiplication operation follows the multiplication(xy) operation specification in the IEE 754-2008 standard.

The FDIV.{S/D} instruction performs the operation that divides the single-precision/double-precision floating-point number in the floating-point register fj by the single-precision/double-precision floating-point number in the floating-point register fk, and writes the result of the single-precision/double-precision floating-point number To the floating-point register fd. The floating-point division operation follows the division(x, y) operation specification in the IEEE 754-2008 standard.

When the operand is a single-precision floating-point number, the upper 32 bits of the resulting floating-point register can be any value.

Instruction formats:

The FMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating point number in floating point register fj with the single-precision/double-precision floating point number in floating point register fk. The result is added to the single-precision/double-precision floating point number in the floating point register fa. The result of the single-precision/double-precision floating point number is written to the floating point register fd

The FMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result minus the floating-point register fa Single-precision/double-precision floating-point numbers, the single-precision/double-precision floating-point number results obtained are written into the floating-point register fd.

The FNMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result plus the single-precision/double-precision floating-point number in the floating-point register fa Precision/double-precision floating-point number, the obtained single-precision/double-precision floating-point number result is negative and written into the floating-point register fd.

The FNMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result minus the floating-point register fa Single-precision/double-precision floating-point number, the result of the single-precision/double-precision floating-point number obtained is negative and written into the floating-point register fd.

The above four floating-point fusion multiply-add operations follow the specification of the fusedMultiplyAdd(xy,z) operation in the IEEE 754-2008 standard.

Instruction formats:

The FMAX.{S/D} instruction selects the larger of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write into the floating-point register fd. The operation of these two instructions follows the specification of maxNum(x,y) operation in the IEEE 754-2008 standard.

The FMIN.{S/D} instruction selects the smaller of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write into the floating-point register fd. The operation of these two instructions follows the minNum(x,y) operation specification in the IEEE 754-2008 standard.

Instruction formats:

The FMAXA.{S/D} instruction selects the larger absolute value of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write to the floating-point register fd. The floating-point addition operation follows the specification of maxNumMag(x.v) operation in IEEE 754-2008 standard.

The FMINA.{S/D} instruction selects the smaller absolute value of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write to the floating-point register fd. The floating-point addition operation follows the specification of minNumMag(x,y) operation in IEEE 754-2008 standard.

Instruction formats:

The FABS.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes its absolute value(that is, the symbol position is 0, and other parts remain unchanged), and writes it into the floating-point register fd. Floating-point addition operations follow the specification of abs(x) operation in the EEE 754-2008 standard.

The FNEG.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes the opposite number(that is, inverts the sign bit, and other parts remain unchanged), and writes it into the floating-point register fd. Floating-point addition operations follow the negate(x) operation specification in the EEE 754-2008 standard.

Instruction formats:

These instructions are operations related to square root and reciprocal.

The FSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, and writes the single-precision/double-precision floating-point number obtained after the square root to the floating-point register fd. The floating-point root operation follows the squareRoot(x) operation specification in the IEEE 754-2008 standard.

The FRECIP.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, divides the floating-point number by 1.0, and writes the resulting single-precision/double-precision floating-point number into the floating-point register fd. It is equivalent to the division(1.0, x) operation in the IEEE 754-2008 standard.

The FRSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes its square root and then divides the obtained single-precision/double-precision floating-point number by 1.0, and the obtained single-precision/double-precision floating-point number is written to the floating-point register fd. The floating-point squared-inverse operation follows the specification of rSqrt(x) operation in IEEE 754-2008 standard.

Instruction formats:

The FSCALEB.{S/D} instruction selects the single-precision/double-precision floating point number a in the floating point register fj, Then take the word/double word integer N in the floating point register fk, and calculate a*2N, The obtained single-precision/double-precision floating point number is written to the floating point register fd. These two instructions follow the IEEE754-2008 standard scaleB(x, N) operation specification.

The FLOGB.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, calculates its logarithm based on 2, and writes the obtained single-precision/double-precision floating-point number into the floating-point register fd . Floating-point exponential operations follow the specification of logB(x) operation in the IEEE 754-2008 standard.

The FCOPYSIGN.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, and changes its sign bit to the sign bit of the single-precision/double-precision floating-point number in the floating-point register fk, and the new one is obtained Single-precision/double-precision floating-point numbers are written into the floating-point register fd. The floating-point copy sign operation follows the specification of copySign(x, y) operation in the IEEE 754-2008 standard.

Instruction formats:

This instruction judges the category of the floating-point number in the floating-point register fj. The result of the judgment is composed of 10 bits of information. The meaning of each bit is shown in the following table:

When the determined data meets the condition corresponding to a certain bit, the corresponding bit of the result information vector will be set to 1. This instruction corresponds to the class(x) function in the IEEE-754-2008 standard.

Instruction formats:

The FRECIPE.{S/D} instruction selects the single-precision or double-precision floating-point number in the floating-point register fj, calculates the single-precision or double-precision floating-point number approximation obtained by dividing the floating-point number by 1.0, and writes the approximation to the floating-point register fd . The relative error of the approximation is less than 2^-14.

When the input value is 2^N, the output value is 2^-N. The results when the input value is QNaN, SNaN, ±∞, ±0, the conditions for generating floating-point exceptions, and the default results when floating-point exceptions are generated without triggering exceptions are the same as those of the FRECIP.{S/D} instruction.

FRSQRTE.{S/D} instruction selects the single/double precision floating point number in the floating point register fj, first extract the Square Root it, and then divides the approximate result by 1.0, and then writes the obtained single/double precision floating point number into the floating point register fd. The relative error of the obtained approximation is less than 2^-14.

When the input value is 2^2N, the output value is 2^-N. The results when the inputs are QNaN, SNaN, ±∞, and ±0, the conditions for generating floating-point exceptions, and the default results when floating-point exceptions are generated but not triggered are the same as those of the FRSQRT.{S/D} instruction.

Instruction formats:

This is a floating-point comparison instruction, which stores the result of the comparison into the specified status code (CC). There are 22 types of cond for this instruction. These comparison conditions and judgment standards are listed in the following table.

Note: UN means no comparison, EQ means equal, IT means less than. When there is at least one NaN in two operands, the two numbers cannot be compared.

Instruction formats:

The FCVT.S.D instruction performs the operation that the double-precision floating-point number in the floating-point register fj to be converted into a single-precision floating-point number, and the obtained single-precision floating-point number is written into the floating-point register fd.

The FCVT.D.S instruction performs the operation that the single-precision floating-point number in the floating-point register fj to be converted into a double-precision floating-point number, and the obtained double-precision floating-point number is written into the floating-point register fd.

The floating-point format conversion operation follows the specification of the convertFormat(x) operation in the IEEE 754-2008 standard.

Instruction formats:

The FFINT{S/D}.{W/L} instruction selects the integer/long-integer fixed-point number in the floating-point register fj and converts it into a single-degree/double-precision floating-point number, and the obtained single-precision/double-precision floating-point number is written to Floating-point register fd. This floating-point format conversion operation follows the convertFromInt(x) operation specification in the EEE 754-2008 standard.

FTINT{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in the floating-point register fj to be converted into an integer/long-integer fixed-point number, and the obtained integer/long-integer fixed-point number is written To the floating-point memory fd. According to the different states in FCSR, the operations in the IEEE 754-2008 standard followed by this floating-point format conversion operation are shown in the following table.

Instruction formats:

These instructions convert floating-point numbers to fixed-point numbers with the specified rounding pattern. FTINTRM.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj and converts it to integer-type long integer-type fixed point number, and the resulting integer-type/long integer-type fixed point number is written to the floating-point register fd, using the “round to negative infinity” mode.

FTINTRP.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, converts it to integer/long-integer fixed point number, and writes the integer/long-integer fixed point number into the floating-point register fd, using the "rounding to positive infinity" method.

FTINTRZ.{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in floating-point register fj, converts it to integer/long-integer fixed-point number, and writes the obtained integer/long-integer fixed-point number to floating-point register fd, using the "rounding to zero" method.

FTINTRNE.{W/L}{S/D} instruction selects the single-precision/double-precision floating-point number in floating-point register fj, converts it to integer long integer fixed point number, and writes the obtained integer/long-integer fixed point number to floating-point register fd, using the "rounding to the nearest even number" method.

The operations in the IEEE 754-2008 standard that the above four floating-point format conversion operations follow are shown in the following table.

Instruction formats:

The FRINT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj and converts it to a single-precision/double-precision floating-point number with integer value, and the resulting single-precision/double-precision floating-point number is written to the floating-point register fd. According to the different states in FCSR, this floating-point format conversion operation follows the operation in IEEE 7542008 standard as shown in the following table.

Instruction formats:

FMOV{S/D} writes the value of the floating-point register fj into the floating-point register fd in the single-precision/double-precision floating-point number format. If the value of fj is not in the single-precision/double-precision floating-point number format, the result is uncertain.

The above instruction operations are non-arithmetic and will not cause IEEE 754 exceptions, nor will they modify the Cause and Flags fields of the floating-point control and status register.

Instruction formats:

The FSEL instruction performs conditional assignment operations.

When FSEL is executed, if the value of the condition flag register ca is equal to 0, the value of the floating-point register fj is written into the floating-point register fd, otherwise the value of the floating-point register fk is written into the floating-point register fd.

Instruction formats:

MOVGR2FR.W writes the low 32-bit value of the general register rj into the low 32-bit of the floating-point register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

MOVGR2FRH.W writes the low 32-bit value of the general register rj into the high 32-bit of the floating-point register fd, and the low 32-bit value of the floating-point register fd remains unchanged.

MOVGR2FR.D writes the 64-bit value of general register rj into floating-point register fd.

Instruction formats:

MOVFR2GRMOVFRH2GR.S sign extensions the low/high 32-bit value of the floating-point register fj and writes it into the general register rd.

MOVFR2GR.D writes the 64-bit value of the floating-point register fj into the general register rd.

Instruction formats:

MOVGR2FCSR modifies the value of the software writable field corresponding to the floating-point control and status register indicated by fcsr according to the value of the lower 32 bits of the general register rj. If the MOVGR2FCSR instruction modifies FCSR0 so that the bits of the Cause field and the corresponding Enables bit are both 1, or modify the Enables field of FCSR1 and the Cause field of FCSR2 so that the Cause bit and the corresponding Enables bit are both 1, the M0VGR2FCSR instruction itself No floating-point exception will be triggered.

MOVFCSR2GR sign extensions the 32-bit value of the floating-point control and status register indicated by fcsr and writes it into the general register rd.

If the floating-point control and status register indicated by fcsr in the above instruction does not exist, the result is uncertain.

Instruction formats:

MOVFR2CF writes the value of the lowest bit of the floating-point register fj into the condition flag register cd.

MOVCF2FR writes the value of the condition flag register cj into the lowest bit of the floating-point register fd.

Instruction formats:

MOVGR2CF writes the value of the lowest bit of the general register rj into the condition flag register cd.

MOVCF2GR writes the value of the condition flag register cj into the lowest bit of the general register rd and clears the other bits.

Instruction formats:

BCEQZ judges the value of the condition flag register cj, if it is equal to 0, jump to the target address, otherwise it does not jump. BCNEZ judges the value of the condition flag register cj, if it is not equal to 0, jump to the target address, otherwise it does not jump. The jump target address of the above two branch instructions is to logically shift the 21-bit immediate offs21 in the instruction code to the left by 2 bits and then sign extension, and the resulting offset value plus the PC of the branch instruction.

Instruction formats:

FLD.S retrieves a word of data from the internal memory and writes it into the lower 32 bits of the floating-point register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

FLD.D retrieves a double word from the internal memory and writes it into the floating-point register fd.

FST.S writes the low 32-bit word data in the floating-point register fd into the memory.

FST.D writes double-word data in the floating-point register fd into the memory.

The access address of the above instruction is calculated by summing the value in the general register rj with the symbolically expanded 12-bit immediate number si12.

FLD.{S/D} and FST.{S/D} instructions, regardless of the hardware implementation and environment configuration, as long as the access address is naturally aligned, the non-alignment exception will not be triggered; when the access address is not naturally aligned, if the hardware implementation supports non-aligned access and the current computing environment is configured to allow non-aligned access, then the non-alignment exception will not be triggered; otherwise, the non-alignment exception will be triggered. Otherwise, the non-alignment exception will be triggered.

Instruction formats:

FLDX.S retrieves a word of data from the memory and writes it into the lower 32 bits of the floating-point register fd. If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

FLDX.D retrieves a double word of data from the memory and writes it into the floating-point register fd.

FSTX.S writes the low 32-bit word data in the floating-point register fd into the memory.

FSTX.D writes the double word data in the floating-point register fd into the memory.

The memory access address calculation method of the above instruction is to add sum the value in the general register rj and the value in the general register rk.

For FLDX.{S/D} and FSTX.{S/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as the memory access address is naturally aligned, the non-aligned exception will not be triggered; When the memory address is not naturally aligned, if the hardware implementation supports unaligned memory access and the current computing environment is configured to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will trigger the unaligned exception.

Instruction formats:

FLD{GT/LE}.{S/D} determines if the valid address is out of bounds and writes the value from memory to the floating-point register.

FLD{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general register rk, and if the condition is met, fetches a word of data from memory and writes it to the lower 32 bits of floating-point register fd. If the floating-point register is 64 bits wide, the high 32-bit value of fd is not determined.

FLD{GT/LE}.D checks if the value in general register rj is greater than/less than/equal to the value in general register rk, and if the condition is met, fetches a double word of data from memory and writes it to floating-point register fd.

FST{GT/LE}.{S/D} determines if the valid address is out of bounds, and writes the value of the floating-point register to memory.

FST{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general register rk, and if the condition is met, writes the low 32-bit word data in floating-point register fd to memory.

FST{GT/LE}.D checks if the value in general register rj is greater than/less than or equal to the value in general register rk, and if the condition is satisfied, writes the double word data in floating-point register fd to memory.

The access address of the above instruction comes directly from the value in general register rj. The access addresses of the above instructions are required to be naturally aligned, otherwise a non-alignment exception will be triggered. The above instruction terminates the access operation and triggers the bound check exception if the check condition is not satisfied.

Instruction formats:

I0CSR{RD/WR}.{B/H/W/D} instructions are used to access the IOCSR.

All IOCSR registers use independent addressing space, and the basic unit of addressing is byte. All data is stored in the IOCSR space in a little-endian storing {B/H/W/D} instruction’s IOCSR address is from the general register rj.

The IOCSRRD.{B/H/W/D} instruction fetches byte/half-word/word/double-word length data from the specified address in the IOCSR space, and writes it to the general register rd after symbolic expansion.

The IOCSRWR.{B/H/W/D} instruction writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data in the general register rd to the beginning of the specified address in the IOCSR space.

The IOCSRRD.D and IOCSRWR.D instructions appear only in LA64.

IOCSR registers can typically be accessed by multiple processor cores simultaneously. The execution of IOCSR access instructions on multiple processor cores satisfies the sequential consistency condition.

Instruction formats:

The CACOP instruction is mainly used for Cache initialization and cache-consistency maintenance.

The value of the general register rj, plus the sign-extended 12-bit immediate number si12, gives the virtual address VA used by the CACOP instruction, which is used to indicate the location of the Cache line being operated on.

Which Cache is accessed by the CACOP instruction and what Cache operation is performed is determined by the 5-bit op in the instruction. op[2:0] indicates the Cache object to be operated on, and op[4:3] indicates the type of operation.

The Cache object indicated by op[2:0] is in the same order as the Cache identified in CPUCFG10. For example, when CPUCFG10=0x02C3D, op[2:0]=0 indicates operation of the first-level private instruction Cache, op[2:0]=1 indicates operation of the first-level private data Cache, op[2:0]=2 indicates operation of the second-level private mixed Cache, and op[2:0]=3 indicates operation of the third-level shared mixed Cache.

op[4:3]=0 is used for Cache initialization (StoreTag), mainly to write the contents of the CSR.CTAG to the tag of the specified Cache row using direct address indexing. Suppose the Cache to be accessed has (1<<Way) ways, each ways has (1<<Index) Cache line, and each Cache line size is (1<<0ffset) bytes, then the direct address indexing method means that the VA[Index+offset1.0ffset] of the VA[Way-1:0] way of the Cache is [operated: 0ffset] line of the Cache.

op[4:3]=1 means that the cache-consistency (Index Invalidate / Invalidate and Writeback) is maintained by direct address indexing. See the previous paragraph for a definition of the direct address indexing method. The operation to maintain consistency is an invalidate and writeback operation on the specified Cache. If the operation is on the instruction Cache, then only the invalidation operation is performed, not the writing back of the data in the Cache row. The data written back into which level of memory is determined by the specific implementation of the Cache hierarchy and the inclusion or mutually exclusive relationship between the levels. For data Cache or mixed Cache, it is up to the implementation to decide whether to write back the data in the Cacche row only if it is dirty.

op[4:3]=2 means that Cache coherency is maintained by query indexing (Hit Invalidate / Invalidate and Writeback).

The operation of maintaining Cache coherency here is the same as described in the above paragraph. The so-called query index approach treats the VA of the CACOP instruction as a normal load instruction to access the Cache to be operated on, and if it hits, it operates on the hit Cache row, otherwise it does not do any operation. Since this query process may involve virtual-to-real address translation, the CACOP instruction may trigger TLB-related exceptions in this case. However, since the CACOP instruction operates on Cache rows, there is no need to consider address alignment or not in this case.

op[4:3]=3 is an implementation of a custom Cache operation and is not explicitly functionally defined in the architecture specification.

Instruction formats:

The functional definition of the TLBSRCH instruction without implementing the LVZ extension is given here.

Use the information of CSR.ASID and CSR.TLBEHI to query TLB. If there is a hit entry, the index of the hit entry is written to the Index field of CSR.TLBIDX, and the INV field of CSR.TLBIDX is set to 0; if there is no hit entry, the INV field of CSR.TLBIDX is set to 1.

The rules for calculating the index of each entry in the TLB are, starting from 0, incremental numbering, first STLB and then MTLB, STLB from the 0th line to the last line of the 0th way, then the 0th line to the last line of the 1st way, until the last line of the last way, MTLB from the 0th line to the last line.

Instruction formats:

The functional definition of the TLBRD instruction without implementing the LVZ extension is given here.

The value of the Index field of CSR.TLBIDX is used as the index to read the specified entry in the TLB. If the specified location is a valid TLB entry, the page table information of the TLB entry is written to CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX.PS, and the INV field of CSR.TLBIDX is set to 0; if the specified location is an invalid TLB entry, then CSR.TLBEHI, CSR.TLBELO0 and CSR.TLBELO1 is set to 0; and the INV field of CSR.TLBIDX is set to 1; TLBIDX.PS is set to 0 and the INV field of CSR.TLBIDX is set to 1.

Note that valid/invalid TLB entries and valid/invalid page table entries in the TLB are two concepts.

If the index used for the access exceeds the range of the TLB, the behavior of the processor is undefinded.

Instruction formats:

The functional definition of the TLBWR instruction without implementing the LVZ extension is given here.

The TLBWR instruction fills the page table entry information stored in the TLB-related CSRs into the TLB. The page table entry information to be populated comes from CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX_PS. If CSR.TLBIDX.NE=1, then the TLB is populated with an invalid TLB entry; only if CSR.TLBIDX.NE=0, the TLB is populated with a valid TLB entry.

The location where the page table entry is written to the TLB is specified by the value of the Index field of CSR.TLBIDX. Please refer to the TLBSRCH instruction for the calculation rules of each index in the TLB for the specific corresponding rules. If a page table entry is to be written to the STLB, but a conflict occurs between the value of the Index field of CSR.TLBIDX and VPPN and CSR.TLBIDX.PS in CSR.TLBEHI, the behavior of the processor is undefinded.

The functional definition of the TLBFILL instruction without implementing the LVZ extension is given here.

The TLBFILL instruction fills the page table entry information stored in the TLB-related CSRs into the TLB. The page table entry information to be populated comes from CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX_PS. If CSR.TLBIDX.NE=1, then the TLB is populated with an invalid TLB entry; only if CSR.TLBIDX.NE=0, the TLB is populated with a valid TLB entry.

Whether to write to STLB or MTLB is first made based on the page size of the page table entry being filled. When the page size of the page table entry being filled is equal to the page size configured for STLB (CSR.STLBPS) it will be filled to STLB, otherwise it will be filled to MTLB. Which way the page table entry is filled to STLB, or which entry is filled to MTLB is randomly selected by the hardware.

Instruction formats:

The contents of the TLB are invalidated according to the information of the TLB-related CSRs to maintain the consistency of the page table data between the TLB and the memory. The functional definition of the TLBCLR instruction without implementing the LVZ extension is given here.

When CSR.index.index falls within the range of MTLB (greater than or equal to the number of STLB entries), TLBCLR is executed to invalidate all page table entries in MTLB with G=0 and ASID equal to CSR.ASID.ASID.

When CSR.index.index falls within the STLB range (less than the number of STLB entries), execute a TLBCLR to invalidate all page table entries in the STLB that are equal to G=0 and ASID equal to CSR.ASID.ASID in the group indicated by the low bit of CSR.index.index.

Instruction formats:

The contents of the TLB are invalidated according to the information of the TLB-related CSRs to maintain the consistency of the page table data between the TLB and the memory. The functional definition of TLBCLR instruction without implementing LVZ extension is given here.

When CSR.index.index falls within the MTLB range (greater than or equal to the number of STLB entries), TLBCLR is executed to invalidate all page table entries in the MTLB.

When CSR.index.index falls within the STLB range (less than the number of STLB entries), a TLBCLR is executed to invalidate all page table entries in the group indicated by the low CSR.index.index in the STLB.

Instruction formats:

The INVTLB instruction is used to invalidate the contents of the TLB to maintain consistency of the page table data between the TLB and memory. The functional definition of the INVTLB instruction is given here for the case where the LVZ extension is not implemented.

Of the three source operands of the instruction, op is a 5-bit immediate number to indicate the type of operation.

The [9:0] bits of the general register rj hold the ASID information required for the invalid operation (called “register specified ASID”), and the remaining bits must be filled with 0. When the operation indicated by op does not require an ASID, the general register rj should be set to r0.

The general register rk is used to store the virtual address information required for invalid operations (called “register specified VA”). When the operation indicated by the op does not require virtual address information, the general register rk should be set to r0.

The operations corresponding to each op are shown in the following table, and the op that does not appear in the table will trigger a reserved instruction exception.

Instruction formats:

The LDDIR instruction is used for accessing directory entries during software page table walking.

The 5-bit immediate level in the LDDIR instruction indicates which page table is currently being accessed. level=1 corresponds to Dir0 in PWCL, level=2 corresponds to Dirl in PWCL, level=3 corresponds to Dir2 in PWCH, and level=4 corresponds to Dir3 in PWCH.

If bit [6] of the general register rj is 0, it means that the content of rj is the physical address of the base address of the level page table at this time. In this case, the LDDIR instruction will access the level page table according to the current TLB refill address, retrieve the base address of the corresponding level+1 page table, and write it to the general register rd.

If bit [6] of general register rj is 1, it means that the content in rj is a large page (Huge Page) page table entry. In this case, after executing the LDDRI instruction, the value in the general register rj will be written directly to the general register rd.

Instruction formats:

The LDPTE instruction is used for page table entry accesses during software page table walking.

The immediate number seq in the LDPTE instruction is used to indicate whether an even or odd number of pages are being accessed. The result is written to CSR.TLBRELO0 when an even page is accessed. The result will be written to CSR.TLBRELO1 when an odd page is accessed.

If bit [6] of the general register rj is 0, the content of rj is the physical address of the base address of the page table at that level of the PTE. In this case, the LDPTE instruction will access the PTE level page table according to the currently processed TLB refill address, retrieve the page table entry and write it to the corresponding CSR.

If bit [6] of the general register rj is 1, it means that the content of rj is a large page (Huge Page) page table entry. In this case, the LDPTE instruction is executed, and the value in general register rj is directly converted into the final page table entry format and written to the corresponding CSR.

Instruction formats:

The ERTN instruction is used to return from exception processing.

If the exception being processed is a debug exception clear the DM bit in the CSR.DEBUG to 0, and jump to the address stored in the CSR.DEBUG to start fetching.

If the exception being processed is something other than a debug exception, update the PPLV, PIE, and PWE information corresponding to the exception to CSR.CRMD, update the PVM in CSR.VMCTL to CSR.VMCTL.VM, and jump to the ERA corresponding to the exception to start fetching instructions.

If the exception processed is an error-related exception, the PPLV, PIE and PWE information corresponding to the exception is from CSR.MERRCTL, and the ERA corresponding to the exception is from CSR.MERRERA. In addition, the PDA, PPG, PDCAF and PDCAM information in CSR.MERRCTL should be updated to CSR.CRMD.

If the exception being processed is a TLB refill exception, the PPLV, PIE, and PWE information corresponding to the exception is from CSR.TLBRPRMD, and the ERA corresponding to the exception is from CSR.TLBRERA. In addition, it is necessary to clear DA field 0 and PG field 1 in CSR.CRMD.

If the exception being handled is not a debug exception, an error-related exception, or a TLB refill exception, then the PPLV, PIE and PWE information corresponding to the exception is from CSR.PRMD, and the ERA corresponding to the exception is from CSR.ERA.

When executing the ERTN instruction, if the KL0 bit in CSR.LLBCTL is not equal to 1, then the LLbit is set to 0, otherwise the LLbit is not modified.